Part Number: AM6422
Hello,
We are observing unexpected interrupt response latency on our system and would like to seek advice.
Setup:
-
A GPS PPS (pulse per second) signal is connected to the capture input pin of Timer 3.
-
Upon entering the capture interrupt, we toggle a GPIO pin and measure the time difference between the GPS pulse edge and the GPIO toggle using a logic analyzer. This difference is taken as the interrupt response latency.
-
We also read the Timer 3 counter value inside the ISR and compare it with the hardware‑captured count value. The maximum difference we observed is over 2000 counts, which translates to about 10 µs (depending on timer clock). We believe the hardware capture itself is accurate, so the delay is caused by interrupt response.
Additional test:
-
We configured a 500 µs periodic timer (Timer 7). In its ISR, we record the current timer count.
-
Theoretically, the count difference between consecutive interrupts should be in the order of nanoseconds. However, in practice, we see a difference of about 2 µs, which indirectly confirms that the timer interrupt response also suffers from latency.
Environment:
-
FreeRTOS is used as the RTOS.
-
The timer interrupt priority is set to 1 (highest, except for critical system interrupts).
-
No other user‑defined interrupts are present in the system besides these timers and tasks.
void AD5711(void) { inter500us[inter500uscnt] = TimerP_getCount(gTimerBaseAddr[CONFIG_TIMER0]); inter500uscnt++; if (inter500uscnt >= 1000) inter500uscnt = 0; } void Timer3_isr0(void *args) { uint32_t value = 0x00; uint32_t timercnt = 0; /* Clear status for overflow interrupt */ value = CSL_REG32_RD(gTimer3BaseAddr + 0x28); if (value & (0x1U << 2)) /* Capture interrupt */ { // GPIO_pinWriteHigh(gpioDO1BaseAddr, CONFIG_DO1_PIN); /* optional toggle */ tim7val = *(uint32_t *)(gTimer7BaseAddr + 0x3c); timercnt = CSL_REG32_RD(gTimer7BaseAddr + 0x50); GPIO_pinWriteLow(gpioDO1BaseAddr, CONFIG_DO1_PIN); } }Questions:
-
Are these latencies expected in a FreeRTOS environment, even with high interrupt priority?
-
Could there be any system overhead (e.g., context saving, cache misses) that causes such delays?
-
How can we further reduce or quantify the interrupt latency?
Any suggestions or insights would be greatly appreciated.
Thank you!
-
