MSPM0L1228-Q1: MSPM DMIPS

Hi Maciej,

We do not explicitly state the DMIPS for our devices; however, the ARM Cortex-M0+ documentation states this:

Performance efficiency: 2.46 CoreMark/MHz * and 0.99/1.30/2.58 DMIPS/MHz **

** The first result abides by all of the “ground rules” laid out in the Dhrystone documentation, the second permits inlining of functions, not just the permitted C string libraries, while the third additionally permits simultaneous (”multi-file”) compilation. All are with the original (K and R) v2.1 of Dhrystone. Arm Compiler 6.17.

Best,

Owen