Part Number: PMP41017
Other Parts Discussed in Thread: TMS320F280039C
Hello,
Planning to implement the PMP41017 reference design from Voltage Mode Control (VMC) to Hybrid Hysteretic Control (HHC).
The PMP41017 schematic includes unpopulated paths routing Phase 1 and Phase 2 SR control to GPIO7 and GPIO11, labeled "optional for CLB SR". However, the provided VMC firmware lacks any CLB initialization. 
As per reference application note spradf4 , mentioned approach uses CLB outputs to internally override the EPWM Action Qualifier (EPWMx_AQ). However, Phase 2 SR on PMP41017 is driven by EPWM6, and the TMS320F280039C does not have a CLB tile mapped to override the EPWM6 AQ.
Could you clarify the designer's intended CLB implementation for these specific pins for SR control of both phases?
Regards,
Nikhil