Part Number: RM48L952
Other Parts Discussed in Thread: RM46L852, , TMDSRM48HDK
Background
I am designing a new device around the Hercules family. Before committing the PCB design, I performed a detailed analysis of the EMIF architecture to identify the most suitable external memory architecture.
Initially I selected the RM46L852, but after studying the EMIF Technical Reference Manual I found an important architectural limitation regarding the asynchronous memory interface.
According to the RM46L852 documentation, the asynchronous EMIF provides:
- 16-bit data bus.
- Up to 13 dedicated EMIF address lines.
- Three asynchronous chip selects.
- Maximum asynchronous address space of 32 KB per chip select.
After analysing the address mapping for 16-bit memories, I understood that:
- EMIF_A provides the address bus.
- EMIF_BA is used to generate the least significant address bit for 16-bit memories.
- Therefore the available address pins only allow the controller to generate addresses covering a 32 KB linear address space for each chip select.
During this analysis I also investigated possible methods to increase the accessible NOR Flash capacity, including:
- GPIO-controlled bank switching.
- External CPLD address translation.
- Automatic bank switching hardware.
However, after analysing the EMIF operation I concluded that every bank transition would still require firmware intervention, since the EMIF itself cannot automatically generate addresses beyond its native address space.
Therefore any external hardware solution would still require firmware support and additional software complexity.
For this reason I decided to evaluate the RM48L952 instead.
RM48L952 EMIF analysis
According to the RM48L952 Technical Reference Manual, the asynchronous EMIF provides:
- 22 dedicated address lines.
- 16-bit data bus.
- Three asynchronous chip selects.
- Up to 16 MiB address space per chip select.
For a x16 NOR Flash, the address mapping becomes:
- BA1 → Flash A0
- EMIF_ADDR[21:0] → Flash A1...A22
This results in:
- 23 effective address bits.
- 2²³ halfwords.
- 2²³ × 2 bytes = 16 MiB
Therefore the entire NOR Flash can be linearly addressed without requiring any bank switching logic or GPIO intervention.
This architectural difference was the main reason for selecting the RM48L952 instead of the RM46L852.
I also analysed the SDRAM controller.
According to the Technical Reference Manual, the SDRAM controller supports:
- One SDRAM chip select.
- 16-bit SDR SDRAM devices.
- One, two or four internal banks.
- 8, 9, 10 or 11 column address bits.
- Up to 128 MiB SDRAM address space.
The controller implements a standard JEDEC SDR SDRAM interface and therefore supports commercially available x16 SDR SDRAM devices.
NOR Flash selection
For firmware storage I selected:
Infineon S29GL128S10DHB020
The reasons are:
- Parallel x16 interface.
- Compatible with the EMIF asynchronous controller.
- Capacity = 128 Mbit (16 MiB).
The selected capacity exactly matches the maximum linear address space provided by one asynchronous chip select on the RM48L952.
Therefore no external bank switching hardware is required.
SDRAM selection
For execution memory I selected:
ISSI IS45S16320F-6BLA1
Reasons:
- SDR SDRAM.
- x16 data bus.
- Four internal banks.
- Capacity = 512 Mbit (64 MiB).
Intended architecture
The intended memory architecture is:
Internal Flash
|
v
Bootloader
|
v
External NOR Flash (16 MiB)
Permanent firmware storage
|
v
Copy during boot
|
v
External SDR SDRAM (64 MiB)
Program execution
Stack
Heap
Global variables
etc
The firmware would be permanently stored in the NOR Flash.
During boot the firmware would be copied into SDRAM.
Afterwards the complete application would execute from SDRAM while the NOR Flash would only be used as non-volatile storage.
Conclusion
Based on the analysis presented above, I believe this memory architecture provides the best compromise between hardware simplicity, software complexity, execution performance and long-term maintainability.
The selected architecture consists of:
- Internal Flash: bootloader and system initialization.
- External NOR Flash (S29GL128S10DHB020): permanent firmware storage.
- External SDR SDRAM (IS45S16320F-6BLA1): application execution after copying the firmware during boot, together with runtime data.
I chose this architecture because current automotive-grade MRAM devices with comparable capacities are still significantly more expensive than SDR SDRAM, making them difficult to justify for this design.
I would greatly appreciate TI's opinion on whether this architecture is appropriate for the RM48L952 EMIF and whether it is consistent with the memory architectures typically recommended or used in Hercules-based designs.
