• State TI Thinks Resolved
  • Locked Locked
  • Replies 2 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 93 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM2612: 2 Deep questions for AM2612

Rio Chan
Genius 16710 points

Part Number: AM2612

Champs.

My cust is concerning those 2 deep quesitons:

Q1. A/B corres concurrently XIP concern.

     (Rio: Let's say R5F has A/B cores.

             So, When A core access the XIP flash , does B core can access the XIP Flahs without waiting A core to finihsed his access?

             Can A and B core access the XIP concurrently but diff region of the XIP flash?


Q2. Interrupt latency on the SRAM vs XIP flash, what's the diff of Latency.
      (Rio:

            Do we have this demo measurement as the below?

             If there is 1 task to have the interrupt waiting from the SRAM or XIP Flash, what's the Latency diff between those 2?

             Any performance result to compare those 2?

 

BR Rio

  • 0
    TI__Guru 62160 points
    Rio Chan said:

    Q1. A/B corres concurrently XIP concern.

         (Rio: Let's say R5F has A/B cores.

                 So, When A core access the XIP flash , does B core can access the XIP Flahs without waiting A core to finihsed his access?

                 Can A and B core access the XIP concurrently but diff region of the XIP flash?

    No One core has to always wait until flash access for the first one is complete since there is only one OSPI BUS.

    ALso It is recomended to to enable XIP from one core only

  • 0
    TI__Guru 62160 points
    Rio Chan said:

    Q2. Interrupt latency on the SRAM vs XIP flash, what's the diff of Latency.
          (Rio:

                Do we have this demo measurement as the below?

                 If there is 1 task to have the interrupt waiting from the SRAM or XIP Flash, what's the Latency diff between those 2?

                 Any performance result to compare those 2?

    INTERRUPTS Should not be placed in external flash