Part Number: AM5726
Hello,
We are debugging an intermittent full A15 hang on an AM572x-based custom board.
System:
- SoC: AM572x / AM5728 custom board
- Cortex-A15 dual core
- Linux on A15_0
- A15_1 used by RTOS
- DSP remains accessible after the failure
- Linux version: TI kernel 4.19.94 RT based SDK
- Failure rate: after hours/days of runtime
Failure description:
After some runtime both A15_0 and A15_1 become inaccessible.
Linux console/network stop responding.
JTAG/CCS shows the A15 cores as running, but they cannot be halted.
Typical CCS error:
"Device failed to enter debug/halt mode because pipeline is stalled"
The DSP is still accessible through JTAG.
We checked the Cortex-A15 identification/errata registers using both CCS CP15 view and a small Linux kernel module reading CP15 registers.
Observed on Linux CPU0:
MIDR = 0x412fc0f2
REVIDR = 0x00000000
ACTLR = 0x00000041
MIDR decode:
- Implementer: 0x41 ARM
- Part: 0xC0F Cortex-A15
- Variant: 0x2 -> r2
- Revision: 0x2 -> p2
REVIDR decode:
- REVIDR[0] 794724 = 0
- REVIDR[1] 799271 = 0
- REVIDR[2] 798870 = 0
- REVIDR[3] 801819 = 0
- REVIDR[4] 798181 = 0
ACTLR decode:
- ACTLR[6] SMP bit = 1
- ACTLR[23] force in-order same set/way = 0
- ACTLR[28:25] write-streaming control = 0x0
- ACTLR[31] snoop-delayed exclusive handling = 0
From the ARM Cortex-A15 r2 errata document, REVIDR bits indicate implementation fixes:
- REVIDR[1] -> erratum 799271: Non-cacheable/streaming writes + DSB + snoop can deadlock
- REVIDR[2] -> erratum 798870: memory read can stall indefinitely in L2 cache
- REVIDR[3] -> erratum 801819: L1 eviction can stall in L2 write buffer preventing snoop completion
Since our REVIDR is 0x00000000, these implementation fixes do not appear to be present in this silicon.
Questions:
1. The register values below were observed in CCS/JTAG under the Cortex-A15 CP15 register view, and were also reproduced from Linux using a small kernel module that reads CP15 directly. MIDR = 0x412fc0f2 REVIDR = 0x00000000 ACTLR = 0x00000041 Can TI confirm whether these reads are valid and reliable for AM572x Cortex-A15 r2p2? 2. What values should we expect on AM572x for the Cortex-A15 revision/errata-related registers, especially REVIDR, ACTLR, L2ACTLR, and ACTLR2? 3. Are there additional TI-recommended ways to validate the Cortex-A15 revision, REVIDR value, and active errata workaround configuration? 4. If any required workaround bits are missing, what is the correct TI-recommended place and method to configure them: SPL/MLO, U-Boot, Linux kernel, Jailhouse, or the RTOS running on A15_1?We would appreciate TI guidance on this.
This is also realted to : https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1657355/am5726-a15-domain-lockup-after-several-days/6409497
I have also attached the A15 errate core version 20
