Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN
The TI TMS570LC4x Silicon Errata document (literature number SPNZ232B) lists an erratum DCAN#27 that reports the issue "Some messages may be placed in the FIFO out of the order in which they were received. If the order of the messages is critical to the application for processing, then this behavior will prevent the proper use of the DCAN FIFO mode."
- Is there any more detailed information you could provide about the conditions under which this errata occurs?
- The workaround listed for the issue is: "Use the DMA to read out the FIFO via the IF3 register. Each time a message is received into the FIFO the data is also copied to the IF3 register and a DMA request is generated to the DMA module to read out the data." HALCoGen does not seem to assist in configuring this workaround, and an example would really help. Could you provide an example implementation? Or at least a DMA CAN sample implementation?
- Is there a technical reference which addresses CAN DMA thoroughly? It seems like the Technical Reference Manual refers to something in the note "Consult your device-specific datasheet to identify the applicability of the DMA-related features..." In the datasheet I could only see a Default DMA Request Map which lists modules and DMA request sources/requests for DCAN, but it's of limited use without some guidance as to how to configure it.
Thank you,
Cameron
