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TMS570LC4357: DCAN#27 erratum questions

Cameron Fruit
Prodigy 65 points

Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

The TI TMS570LC4x Silicon Errata document (literature number SPNZ232B) lists an erratum DCAN#27 that reports the issue "Some messages may be placed in the FIFO out of the order in which they were received. If the order of the messages is critical to the application for processing, then this behavior will prevent the proper use of the DCAN FIFO mode." 

  1. Is there any more detailed information you could provide about the conditions under which this errata occurs? 
  2. The workaround listed for the issue is: "Use the DMA to read out the FIFO via the IF3 register. Each time a message is received into the FIFO the data is also copied to the IF3 register and a DMA request is generated to the DMA module to read out the data."  HALCoGen does not seem to assist in configuring this workaround, and an example would really help. Could you provide an example implementation? Or at least a DMA CAN sample implementation?
  3. Is there a technical reference which addresses CAN DMA thoroughly? It seems like the Technical Reference Manual refers to something in the note "Consult your device-specific datasheet to identify the applicability of the DMA-related features..." In the datasheet I could only see a Default DMA Request Map which lists modules and DMA request sources/requests for DCAN, but it's of limited use without some guidance as to how to configure it.

Thank you,

Cameron

  • 0 in reply to QJ Wang
    Prodigy 65 points

    Thanks QJ for your reply, but loading that URL gives me an error message: "Unfortunately, the page you've requested no longer exists. Please use the search form above to locate the information you're interested in."

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    Here is an example of IF3+DMA on LS0914 device. You can use the same way for LC4357.

    When a CAN message lands in the Message RAM, the hardware itself dumps the data directly into the IF3 register set without needing any manual CPU command. Because the CPU isn't actively querying the Message RAM via IF1/IF2, the internal message arbitration pointer avoids the race condition entirely

    TMS570LS0914PZ_DCAN_IF3_DMA.zip

  • 0 in reply to QJ Wang
    Prodigy 65 points

    Thanks for this, QJ. 

    What I’d really like is to understand the DCAN#27 issue more clearly. The description of the erratum in spnz232b.pdf only says, “DCAN operates in FIFO mode and uses the CPU to read out the data.” It seems like there must be some more specific conditions that cause messages to be placed in the FIFO out of order. Is there any additional information that you can share?

     We’ve not noticed any out-of-order messages in our testing, so we suspect we may be able to rule out this issue. 

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    Hi Cameron,

    I don't have the detailed information for DCAN #27.

  • 0 in reply to QJ Wang
    Prodigy 65 points

    FYI: I was able to acquire some additional information from a different source:

    1. The CPU is reading a Message Object via the Interface Registers (IF1, IF2) to pull data out of the FIFO. 
    2. Simultaneously, a new CAN frame arrives over the network.
    3. The internal DCAN message handler scans the message RAM to find the next available slot in the FIFO to store the new incoming frame.

    Because the CPU is mid-read, the internal state machine incorrectly reads the NewDat flags of the active message objects during its arbitration cycle. The DCAN internal handler incorrectly concludes that a higher-indexed mailbox is available, skips the true logical sequentially-next mailbox, and dumps the incoming frame into a slot further down the line. Consequently, messages appear out of chronological order, or a valid message gets trapped behind an un-cleared mailbox, stalling the FIFO logic.

    This issue is a race condition cause by the lack of synchronization between CPU and the DCAN internal state machine. Specifically, the collision occurs when the CPU is performing a read operation via the Interface Registers (IF1/IF2) at the exact moment the DCAN hardware is executing its internal arbitration cycle to find an available Message RAM slot for an incoming frame. Because the hardware fails to correctly arbitrate the NewDat flags while a CPU read is in process, the internal pointer can skip the logically next mailbox, resulting in out-of-order message placement or FIFO stalling.

    -------

    This additional information confirmed that it is needful for me to implement the recommended workaround. Unfortunately I have not been able to get this to work. My goal is to use DMA to read received CAN messages from IF3 registers (specifically DATA and DATAB) of DCAN1, 2, 3, and 4. The message boxes that are configured for receiving are #1-16.

    I can't list my code, but currently my implementation is doing the following:

    - Set bit 20 of the CTL register for DCAN1, 2, 3, and 4 to enable DMA request for IF3.

    - Set OBS register for DCAN1, 2, 3, and 4 to 0x18 to require reading DATA and DATB to enable next IF3 update.

    - Set IF3 Update Enable registers for DCAN1, 2, 3, and 4 to 0x0000FFFF.

    - Created 8-byte arrays for use as a destination by DMA for DCAN1, 2, 3, and 4.

    - Enabled DMA.

    - Assigned DMA requests #16, 4, 21, 47. (Is this step necessary?)

    - Configure DMA configuration control Rx packet for IF3 on each DCAN channel:

      * source address from the IR3DATx

      * destination address from an 8-byte array

      * element count 1

      * read size and write size both 64 bits

      * port B read, port A write assignments

      * frame transfer type

      * fixed read/write addresses

      * auto init off

    - Set the DMA control packets in DMA RAM.

    - Set port assignment in DMA PAR# register.

    - Enable DMA interrupt for configured channels.

    - Enabled channel for software/hardware triggering (I've tried both without success).

    When I execute this and send CAN traffic (on DCAN4), I can see the first message populating IF3, but DMA does not respond by writing the message data to the 8-byte arrays, which is what I expected. Could you please help me identify what I'm missing to force DMA to access IF3 and copy to the arrays I've configured?

    Thanks for any guidance you can provide.

    Cameron

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points
    Cameron Fruit said:
    Assigned DMA requests #16, 4, 21, 47. (Is this step necessary?)

    It is to assign DMA request lines for DCAN1/2/3/4 to DMA channels. Yes, it is needed.

    Cameron Fruit said:
    - Set port assignment in DMA PAR# register.

    What value did you program to PARx register? IF3x is only for reading data. So the operation is to read data from DCAN, then write to SRAM. I suggest 0x0 for PARx

  • 0 in reply to QJ Wang
    Prodigy 65 points

    I set PARx to 0x0.

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    The TMS570 interrupt structure has three layers:

    1. Peripheral level (enables the specific hardware event)

    2. VIM level (manages and prioritizes channels)

    3. CPU Core level (globally enables IRQ/FIQ via the CPSR

    Have you enabled the IRQ interrupt?

        _enable_interrupt_();
    Did you enable the VIM channels for DCAN?
  • 0 in reply to QJ Wang
    Prodigy 65 points

    I have enabled the IRQ interrupt in the _enable_interrupt_ function with the instruction "cpsie if".

    I was not enabling the VIM channels for DCAN, as we have a periodic function reading the messages instead of using an routine servicing the CAN interrupts to read them. Is it required to enable the VIM channels so that DMA knows when to read of IF3 data? I tried it just now but DMA was still not doing anything.

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    The data has been transferred from message RAM to IF3 data register, so the CAN config should be fine. 

    Please double check:

    1. assign DMA request to DMA channel:

    dmaReqAssign(DMA_CH0, 47);  //for DCAN4, request line s 47
    2. source address and destination addr at 0xFFF80000h
    3
    Cameron Fruit said:
      * port B read, port A write assignments

    can you try 0x4 instead of 0x0? 

    g_dmaCTRLPKT.PORTASGN  = 4;                 /* port b    
  • 0 in reply to QJ Wang
    Prodigy 65 points

    Hi QJ,

    Thanks for these troubleshooting ideas.

    1. I assign the DMA request as you indicated except I'm using a different channel:

    dmaReqAssign(DMA_CH4, 47);

    The DREQASI1 register has 2F in bits 24-29 as expected.

    2. Initial source address for DCAN 4 IF3DATA is 0xFFF7E350. Destination address matches the base of my read array (0x0806AE0C).

    3. The behavior is apparently the same using 0x4 or 0x0.

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    The OBS register is configured correctly (0x18), and the IF3UPDx registers are mapped to target message boxes (#1-16). Ypu also have assigned the DMA request to DMA channel.

    Have you enabled the DMA HW trigger? for example:
    dmaSetChEnable(DMA_CH0, DMA_HW);

  • 0 in reply to QJ Wang
    Prodigy 65 points

    Yes, I have already enabled the DMA HW trigger by writing 1 to the corresponding bit in the DMA HWCHENAS register. What else could I be missing?

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    I'd like to make sure that the data in FIFO is transferred to IF3x data register automatically whenever the CAN receives a message.

    Can you dump the value of DCAN registers and DMA registers?

  • 0 in reply to QJ Wang
    Prodigy 65 points

    First, here are the values of the DCAN registers and DMA registers after configuration, but prior to receiving any CAN messages:

    R Dcan4_CTL 0x0000000B 0x00121602
    R Dcan4_ES 0x0000000B 0x00000063
    R Dcan4_ERRC 0x0000000B 0x00000080
    R Dcan4_BTR 0x0000000B 0x00000707
    R Dcan4_INT 0x0000000B 0x00000000
    R Dcan4_TEST 0x0000000B 0x00000000
    R Dcan4_PERR 0x0000000B 0x00000048
    R Dcan4_REL 0x0000000B 0xA3170504
    R Dcan4_ECCDIAG 0x0000000B 0x0000000A
    R Dcan4_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan4_ECC_CS 0x0000000B 0x050A0000
    R Dcan4_ECC_SERR 0x0000000B 0x00000000
    R Dcan4_ABOTR 0x0000000B 0x047868C0
    R Dcan4_TXRQX 0x0000000B 0x00000004
    R Dcan4_TXRQ12 0x0000000B 0x00030000
    R Dcan4_TXRQ34 0x0000000B 0x00000000
    R Dcan4_TXRQ56 0x0000000B 0x00000000
    R Dcan4_TXRQ78 0x0000000B 0x00000000
    R Dcan4_NWDATX 0x0000000B 0x00000004
    R Dcan4_NWDAT12 0x0000000B 0x00020000
    R Dcan4_NWDAT34 0x0000000B 0x00000000
    R Dcan4_NWDAT56 0x0000000B 0x00000000
    R Dcan4_NWDAT78 0x0000000B 0x00000000
    R Dcan4_INTPNDX 0x0000000B 0x00000000
    R Dcan4_INTPND12 0x0000000B 0x00000000
    R Dcan4_INTPND34 0x0000000B 0x00000000
    R Dcan4_INTPND56 0x0000000B 0x00000000
    R Dcan4_INTPND78 0x0000000B 0x00000000
    R Dcan4_MSGVALX 0x0000000B 0x000000FF
    R Dcan4_MSGVAL12 0x0000000B 0xFFFFFFFF
    R Dcan4_MSGVAL34 0x0000000B 0xFFFFFFFF
    R Dcan4_MSGVAL56 0x0000000B 0x00000000
    R Dcan4_MSGVAL78 0x0000000B 0x00000000
    R Dcan4_INTMUX12 0x0000000B 0x00000000
    R Dcan4_INTMUX34 0x0000000B 0x00000000
    R Dcan4_INTMUX56 0x0000000B 0x00000000
    R Dcan4_INTMUX78 0x0000000B 0x00000000
    R Dcan4_IF1CMD 0x0000000B 0x00FF0012
    R Dcan4_IF1MSK 0x0000000B 0xE0000000
    R Dcan4_IF1ARB 0x0000000B 0xE869A240
    R Dcan4_IF1MCTL 0x0000000B 0x00001088
    R Dcan4_IF1DATA 0x0000000B 0xEF0A1010
    R Dcan4_IF1DATB 0x0000000B 0x0B01EA0A
    R Dcan4_IF2CMD 0x0000000B 0x00370040
    R Dcan4_IF2MSK 0x0000000B 0xE00007FF
    R Dcan4_IF2ARB 0x0000000B 0xE0000040
    R Dcan4_IF2MCTL 0x0000000B 0x00001088
    R Dcan4_IF2DATA 0x0000000B 0x00000000
    R Dcan4_IF2DATB 0x0000000B 0x00000000
    R Dcan4_IF3OBS 0x0000000B 0x00000018
    R Dcan4_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan4_IF3ARB 0x0000000B 0x00000000
    R Dcan4_IF3MCTL 0x0000000B 0x00000000
    R Dcan4_IF3DATA 0x0000000B 0x00000000
    R Dcan4_IF3DATB 0x0000000B 0x00000000
    R Dcan4_IF3UPD12 0x0000000B 0x0000FFFF
    R Dcan4_IF3UPD34 0x0000000B 0x00000000
    R Dcan4_IF3UPD56 0x0000000B 0x00000000
    R Dcan4_IF3UPD78 0x0000000B 0x00000000
    R Dcan4_TIOC 0x0000000B 0x0004000C
    R Dcan4_RIOC 0x0000000B 0x00040009
    R Dcan3_CTL 0x0000000B 0x00001401
    R Dcan3_ES 0x0000000B 0x00000007
    R Dcan3_ERRC 0x0000000B 0x00000000
    R Dcan3_BTR 0x0000000B 0x00002301
    R Dcan3_INT 0x0000000B 0x00000000
    R Dcan3_TEST 0x0000000B 0x00000080
    R Dcan3_PERR 0x0000000B 0x00000000
    R Dcan3_REL 0x0000000B 0xA3170504
    R Dcan3_ECCDIAG 0x0000000B 0x0000000A
    R Dcan3_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan3_ECC_CS 0x0000000B 0x050A0000
    R Dcan3_ECC_SERR 0x0000000B 0x00000000
    R Dcan3_ABOTR 0x0000000B 0x00000000
    R Dcan3_TXRQX 0x0000000B 0x00000000
    R Dcan3_TXRQ12 0x0000000B 0x00000000
    R Dcan3_TXRQ34 0x0000000B 0x00000000
    R Dcan3_TXRQ56 0x0000000B 0x00000000
    R Dcan3_TXRQ78 0x0000000B 0x00000000
    R Dcan3_NWDATX 0x0000000B 0x00000000
    R Dcan3_NWDAT12 0x0000000B 0x00000000
    R Dcan3_NWDAT34 0x0000000B 0x00000000
    R Dcan3_NWDAT56 0x0000000B 0x00000000
    R Dcan3_NWDAT78 0x0000000B 0x00000000
    R Dcan3_INTPNDX 0x0000000B 0x00000000
    R Dcan3_INTPND12 0x0000000B 0x00000000
    R Dcan3_INTPND34 0x0000000B 0x00000000
    R Dcan3_INTPND56 0x0000000B 0x00000000
    R Dcan3_INTPND78 0x0000000B 0x00000000
    R Dcan3_MSGVALX 0x0000000B 0x00000000
    R Dcan3_MSGVAL12 0x0000000B 0x00000000
    R Dcan3_MSGVAL34 0x0000000B 0x00000000
    R Dcan3_MSGVAL56 0x0000000B 0x00000000
    R Dcan3_MSGVAL78 0x0000000B 0x00000000
    R Dcan3_INTMUX12 0x0000000B 0x00000000
    R Dcan3_INTMUX34 0x0000000B 0x00000000
    R Dcan3_INTMUX56 0x0000000B 0x00000000
    R Dcan3_INTMUX78 0x0000000B 0x00000000
    R Dcan3_IF1CMD 0x0000000B 0x00000001
    R Dcan3_IF1MSK 0x0000000B 0xFFFFFFFF
    R Dcan3_IF1ARB 0x0000000B 0x00000000
    R Dcan3_IF1MCTL 0x0000000B 0x00000000
    R Dcan3_IF1DATA 0x0000000B 0x00000000
    R Dcan3_IF1DATB 0x0000000B 0x00000000
    R Dcan3_IF2CMD 0x0000000B 0x00000001
    R Dcan3_IF2MSK 0x0000000B 0xFFFFFFFF
    R Dcan3_IF2ARB 0x0000000B 0x00000000
    R Dcan3_IF2MCTL 0x0000000B 0x00000000
    R Dcan3_IF2DATA 0x0000000B 0x00000000
    R Dcan3_IF2DATB 0x0000000B 0x00000000
    R Dcan3_IF3OBS 0x0000000B 0x00000000
    R Dcan3_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan3_IF3ARB 0x0000000B 0x00000000
    R Dcan3_IF3MCTL 0x0000000B 0x00000000
    R Dcan3_IF3DATA 0x0000000B 0x00000000
    R Dcan3_IF3DATB 0x0000000B 0x00000000
    R Dcan3_IF3UPD12 0x0000000B 0x00000000
    R Dcan3_IF3UPD34 0x0000000B 0x00000000
    R Dcan3_IF3UPD56 0x0000000B 0x00000000
    R Dcan3_IF3UPD78 0x0000000B 0x00000000
    R Dcan3_TIOC 0x0000000B 0x00040001
    R Dcan3_RIOC 0x0000000B 0x00040001
    R Dcan2_CTL 0x0000000B 0x00001401
    R Dcan2_ES 0x0000000B 0x00000007
    R Dcan2_ERRC 0x0000000B 0x00000000
    R Dcan2_BTR 0x0000000B 0x00002301
    R Dcan2_INT 0x0000000B 0x00000000
    R Dcan2_TEST 0x0000000B 0x00000080
    R Dcan2_PERR 0x0000000B 0x0000007A
    R Dcan2_REL 0x0000000B 0xA3170504
    R Dcan2_ECCDIAG 0x0000000B 0x0000000A
    R Dcan2_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan2_ECC_CS 0x0000000B 0x050A0000
    R Dcan2_ECC_SERR 0x0000000B 0x00000044
    R Dcan2_ABOTR 0x0000000B 0x00000000
    R Dcan2_TXRQX 0x0000000B 0x00000000
    R Dcan2_TXRQ12 0x0000000B 0x00000000
    R Dcan2_TXRQ34 0x0000000B 0x00000000
    R Dcan2_TXRQ56 0x0000000B 0x00000000
    R Dcan2_TXRQ78 0x0000000B 0x00000000
    R Dcan2_NWDATX 0x0000000B 0x00000000
    R Dcan2_NWDAT12 0x0000000B 0x00000000
    R Dcan2_NWDAT34 0x0000000B 0x00000000
    R Dcan2_NWDAT56 0x0000000B 0x00000000
    R Dcan2_NWDAT78 0x0000000B 0x00000000
    R Dcan2_INTPNDX 0x0000000B 0x00000000
    R Dcan2_INTPND12 0x0000000B 0x00000000
    R Dcan2_INTPND34 0x0000000B 0x00000000
    R Dcan2_INTPND56 0x0000000B 0x00000000
    R Dcan2_INTPND78 0x0000000B 0x00000000
    R Dcan2_MSGVALX 0x0000000B 0x00000000
    R Dcan2_MSGVAL12 0x0000000B 0x00000000
    R Dcan2_MSGVAL34 0x0000000B 0x00000000
    R Dcan2_MSGVAL56 0x0000000B 0x00000000
    R Dcan2_MSGVAL78 0x0000000B 0x00000000
    R Dcan2_INTMUX12 0x0000000B 0x00000000
    R Dcan2_INTMUX34 0x0000000B 0x00000000
    R Dcan2_INTMUX56 0x0000000B 0x00000000
    R Dcan2_INTMUX78 0x0000000B 0x00000000
    R Dcan2_IF1CMD 0x0000000B 0x00000001
    R Dcan2_IF1MSK 0x0000000B 0xFFFFFFFF
    R Dcan2_IF1ARB 0x0000000B 0x00000000
    R Dcan2_IF1MCTL 0x0000000B 0x00000000
    R Dcan2_IF1DATA 0x0000000B 0x00000000
    R Dcan2_IF1DATB 0x0000000B 0x00000000
    R Dcan2_IF2CMD 0x0000000B 0x00000001
    R Dcan2_IF2MSK 0x0000000B 0xFFFFFFFF
    R Dcan2_IF2ARB 0x0000000B 0x00000000
    R Dcan2_IF2MCTL 0x0000000B 0x00000000
    R Dcan2_IF2DATA 0x0000000B 0x00000000
    R Dcan2_IF2DATB 0x0000000B 0x00000000
    R Dcan2_IF3OBS 0x0000000B 0x00000000
    R Dcan2_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan2_IF3ARB 0x0000000B 0x00000000
    R Dcan2_IF3MCTL 0x0000000B 0x00000000
    R Dcan2_IF3DATA 0x0000000B 0x00000000
    R Dcan2_IF3DATB 0x0000000B 0x00000000
    R Dcan2_IF3UPD12 0x0000000B 0x00000000
    R Dcan2_IF3UPD34 0x0000000B 0x00000000
    R Dcan2_IF3UPD56 0x0000000B 0x00000000
    R Dcan2_IF3UPD78 0x0000000B 0x00000000
    R Dcan2_TIOC 0x0000000B 0x00040001
    R Dcan2_RIOC 0x0000000B 0x00040001
    R Dcan1_CTL 0x0000000B 0x00001401
    R Dcan1_ES 0x0000000B 0x00000007
    R Dcan1_ERRC 0x0000000B 0x00000000
    R Dcan1_BTR 0x0000000B 0x00002301
    R Dcan1_INT 0x0000000B 0x00000000
    R Dcan1_TEST 0x0000000B 0x00000080
    R Dcan1_PERR 0x0000000B 0x00000000
    R Dcan1_REL 0x0000000B 0xA3170504
    R Dcan1_ECCDIAG 0x0000000B 0x0000000A
    R Dcan1_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan1_ECC_CS 0x0000000B 0x050A0000
    R Dcan1_ECC_SERR 0x0000000B 0x00000000
    R Dcan1_ABOTR 0x0000000B 0x00000000
    R Dcan1_TXRQX 0x0000000B 0x00000000
    R Dcan1_TXRQ12 0x0000000B 0x00000000
    R Dcan1_TXRQ34 0x0000000B 0x00000000
    R Dcan1_TXRQ56 0x0000000B 0x00000000
    R Dcan1_TXRQ78 0x0000000B 0x00000000
    R Dcan1_NWDATX 0x0000000B 0x00000000
    R Dcan1_NWDAT12 0x0000000B 0x00000000
    R Dcan1_NWDAT34 0x0000000B 0x00000000
    R Dcan1_NWDAT56 0x0000000B 0x00000000
    R Dcan1_NWDAT78 0x0000000B 0x00000000
    R Dcan1_INTPNDX 0x0000000B 0x00000000
    R Dcan1_INTPND12 0x0000000B 0x00000000
    R Dcan1_INTPND34 0x0000000B 0x00000000
    R Dcan1_INTPND56 0x0000000B 0x00000000
    R Dcan1_INTPND78 0x0000000B 0x00000000
    R Dcan1_MSGVALX 0x0000000B 0x00000000
    R Dcan1_MSGVAL12 0x0000000B 0x00000000
    R Dcan1_MSGVAL34 0x0000000B 0x00000000
    R Dcan1_MSGVAL56 0x0000000B 0x00000000
    R Dcan1_MSGVAL78 0x0000000B 0x00000000
    R Dcan1_INTMUX12 0x0000000B 0x00000000
    R Dcan1_INTMUX34 0x0000000B 0x00000000
    R Dcan1_INTMUX56 0x0000000B 0x00000000
    R Dcan1_INTMUX78 0x0000000B 0x00000000
    R Dcan1_IF1CMD 0x0000000B 0x00000001
    R Dcan1_IF1MSK 0x0000000B 0xFFFFFFFF
    R Dcan1_IF1ARB 0x0000000B 0x00000000
    R Dcan1_IF1MCTL 0x0000000B 0x00000000
    R Dcan1_IF1DATA 0x0000000B 0x00000000
    R Dcan1_IF1DATB 0x0000000B 0x00000000
    R Dcan1_IF2CMD 0x0000000B 0x00000001
    R Dcan1_IF2MSK 0x0000000B 0xFFFFFFFF
    R Dcan1_IF2ARB 0x0000000B 0x00000000
    R Dcan1_IF2MCTL 0x0000000B 0x00000000
    R Dcan1_IF2DATA 0x0000000B 0x00000000
    R Dcan1_IF2DATB 0x0000000B 0x00000000
    R Dcan1_IF3OBS 0x0000000B 0x00000000
    R Dcan1_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan1_IF3ARB 0x0000000B 0x00000000
    R Dcan1_IF3MCTL 0x0000000B 0x00000000
    R Dcan1_IF3DATA 0x0000000B 0x00000000
    R Dcan1_IF3DATB 0x0000000B 0x00000000
    R Dcan1_IF3UPD12 0x0000000B 0x00000000
    R Dcan1_IF3UPD34 0x0000000B 0x00000000
    R Dcan1_IF3UPD56 0x0000000B 0x00000000
    R Dcan1_IF3UPD78 0x0000000B 0x00000000
    R Dcan1_TIOC 0x0000000B 0x00040001
    R Dcan1_RIOC 0x0000000B 0x00040001

    Dma
    [0 ... 99]
    GlbCtrl 0x00010300 Global Control Register [Memory Mapped]
    ChnPnd 0x00010002 Channel Pending Register [Memory Mapped]
    Stat 0x00000000 Status Register [Memory Mapped]
    HWChnEnaSet 0x0000001D H/W Channel Enable Set and Status Register [Memory Mapped]
    HWChnEnaRst 0x0000001D H/W Channel Enable Reset and Status Register [Memory Mapped]
    SWChnEnaSet 0x00000000 S/W Channel Enable Set and Status Register [Memory Mapped]
    SWChnEnaRst 0x00000000 S/W Channel Enable Reset and Status Register [Memory Mapped]
    ChnPrioSet 0x00000000 Channel Priority Set Register [Memory Mapped]
    ChnPrioRst 0x00000000 Channel Priority Reset [Memory Mapped]
    GlbChnIntEnaSet 0x0000001F Global Channel Interrupt Enable Set [Memory Mapped]
    GlbChnIntEnaRst 0x0000001F Global Channel Interrupt Enable Reset [Memory Mapped]
    ReqAssg0 0x10100415 Request Assignment Register 0 [Memory Mapped]
    ReqAssg1 0x2F050607 Request Assignment Register 1 [Memory Mapped]
    ReqAssg2 0x08090A0B Request Assignment Register 2 [Memory Mapped]
    ReqAssg3 0x0C0D0E0F Request Assignment Register 3 [Memory Mapped]
    ReqAssg4 0x10111213 Request Assignment Register 4 [Memory Mapped]
    ReqAssg5 0x14151617 Request Assignment Register 5 [Memory Mapped]
    ReqAssg6 0x18191A1B Request Assignment Register 6 [Memory Mapped]
    ReqAssg7 0x1C1D1E1F Request Assignment Register 7 [Memory Mapped]
    PrtAssg0 0x04444000 Port Assignment Register 0 [Memory Mapped]
    PrtAssg1 0x00000000 Port Assignment Register 1 [Memory Mapped]
    PrtAssg2 0x00000000 Port Assignment Register 2 [Memory Mapped]
    PrtAssg3 0x00000000 Port Assignment Register 3 [Memory Mapped]
    FTCMap 0x00000000 FTC Interrupt Mapping Register [Memory Mapped]
    LFSMap 0x00000000 LFS Interrupt Mapping Register [Memory Mapped]
    HBCMap 0x00000000 HBC Interrupt Mapping Register [Memory Mapped]
    BTCMap 0x00000000 BTC Interrupt Mapping Register [Memory Mapped]
    BERMap 0x00000000 BER Interrupt Mapping Register [Memory Mapped]
    FTCIntEnaSet 0x0000001F FTC Interrupt Enable Set [Memory Mapped]
    FTCIntEnaRst 0x0000001F FTC Interrupt Enable Reset [Memory Mapped]
    LFSIntEnaSet 0x00000000 LFS Interrupt Enable Set [Memory Mapped]
    LFSIntEnaRst 0x00000000 LFS Interrupt Enable Reset [Memory Mapped]
    HBCIntEnaSet 0x00000000 HBC Interrupt Enable Set [Memory Mapped]
    HBCIntEnaRst 0x00000000 HBC Interrupt Enable Reset [Memory Mapped]
    BTCIntEnaSet 0x00000000 BTC Interrupt Enable Set [Memory Mapped]
    BTCIntEnaRst 0x00000000 BTC Interrupt Enable Reset [Memory Mapped]
    GlbIntFlg 0x00000003 Global Interrupt Flg Register [Memory Mapped]
    FTCIntFlg 0x00000001 FTC Interrupt Flag Register [Memory Mapped]
    LFSIntFlg 0x00000003 LFS Interrupt Flag Register [Memory Mapped]
    HBCIntFlg 0x00000000 HBC Interrupt Flag Register [Memory Mapped]
    BTCIntFlg 0x00000003 BER Interrupt Flag Register [Memory Mapped]
    BERIntFlg 0x00000000 BER Interrupt Flag Register [Memory Mapped]
    FTCAOffst 0x00000001 FTCA Interrupt Channel Offset Register [Memory Mapped]
    LFSAOffst 0x00000000 LFSA Interrupt Channel Offset Register [Memory Mapped]
    HBCAOffst 0x00000000 HBCA Interrupt Channel Offset Register [Memory Mapped]
    BTCAOffst 0x00000000 BTCA Interrupt Channel Offset Register [Memory Mapped]
    BERAOffst 0x00000000 BERA Interrupt Channel Offset Register [Memory Mapped]
    FTCBOffst 0x00000000 FTCB Interrupt Channel Offset Register [Memory Mapped]
    LSFBOffst 0x00000000 LFSB Interrupt Channel Offset Register [Memory Mapped]
    HBCBOffst 0x00000000 HBCB Interrupt Channel Offset Register [Memory Mapped]
    BTCBOffst 0x00000000 BTCB Interrupt Channel Offset Register [Memory Mapped]
    BERBOffst 0x00000000 BERB Interrupt Channel Offset Register [Memory Mapped]
    PrtCtrl 0x00000000 Port Control Register [Memory Mapped]
    RamTstCtrl 0x00000000 RAM TEST Control [Memory Mapped]
    DbgCtrl 0x00000000 Debug Control [Memory Mapped]
    WpReg 0x00000000 Watchpoint Register [Memory Mapped]
    WpMsk 0x00000000 Watchpoint Mask Register [Memory Mapped]
    PrtAChnSrcAddr 0xFFF7C2B0 Port A Active Channel Source Address Register [Memory Mapped]
    PrtAChnDstAddr 0x0807F024 Port A Active Channel Destination Address Register [Memory Mapped]
    PrtAChnTrCnt 0x00000000 Port A Active Channel Transfer Count Register [Memory Mapped]
    PrtBChnSrcAddr 0xFFF7DD50 Port B Active Channel Source Address Register [Memory Mapped]
    PrtBChnDestAddr 0x0806ADF4 Port B Active Channel Destination Address Register [Memory Mapped]
    PrtBChnTrCnt 0x00000000 Port B Active Channel Transfer Count Register [Memory Mapped]
    ParCtrl 0x00000005 Parity Control Register [Memory Mapped]
    ParErrAddr 0x0000016C Parity Error Address Register [Memory Mapped]
    MpCtrl 0x00000000 Memory Protection Control Register [Memory Mapped]
    MpStat 0x00000000 Memory Protection Status Register [Memory Mapped]
    Pr0Strt 0x00000000 Start Address of region 0 [Memory Mapped]
    Pr0End 0x00000000 End Address of region 0 [Memory Mapped]
    Pr1Strt 0x00000000 Start Address of region 0 [Memory Mapped]
    Pr1End 0x00000000 End Address of region 1 [Memory Mapped]
    Pr2Strt 0x00000000 Start Address of region 2 [Memory Mapped]
    Pr2End 0x00000000 End Address of region 2 [Memory Mapped]
    Pr3Strt 0x00000000 Start Address of region 3 [Memory Mapped]
    Pr3End 0x00000000 End Address of region 3 [Memory Mapped]
    MpCtrl2 0x00000000 Memory Protection Control Register2 [Memory Mapped]
    MpStat2 0x00000000 Memory Protection Status Register2 [Memory Mapped]
    Pr4Strt 0x00000000 Start Address of region 4 [Memory Mapped]
    Pr4End 0x00000000 End Address of region 4 [Memory Mapped]
    Pr5Strt 0x00000000 Start Address of region 5 [Memory Mapped]
    Pr5End 0x00000000 End Address of region 5 [Memory Mapped]
    Pr6Strt 0x00000000 Start Address of region 6 [Memory Mapped]
    Pr6End 0x00000000 End Address of region 6 [Memory Mapped]
    Pr7Strt 0x00000000 Start Address of region 7 [Memory Mapped]
    Pr7End 0x00000000 End Address of region 7 [Memory Mapped]
    PFCtrl 0x00050000 Pattern Fill Control Register [Memory Mapped]
    UPFReg 0x00000000 Upper Pattern Fill Register [Memory Mapped]
    LPFReg 0x00000000 Lower Pattern Fill Register [Memory Mapped]
    PMCtrl 0x00050000 Pattern Mask Control Register [Memory Mapped]
    UPMReg 0x00000000 Upper Pattern Mask Register [Memory Mapped]
    LPMReg 0x00000000 Lower Pattern Mask Register [Memory Mapped]
    CullConReg 0x05000000 Cull Configuration Register [Memory Mapped]
    SEccCtrl 0x0000050A Single Bit ECC Control Register [Memory Mapped]
    SEccAddr 0x0000000C Single Bit ECC Error Address Register [Memory Mapped]
    FifoAStat 0x00000000 Fifo A Status Register [Memory Mapped]
    FifoBStat 0x00000000 Fifo B Status Register [Memory Mapped]
    FTCMap0 0x00000000 FTC Interrupt Mapping Register 0 [Memory Mapped]
    FTCMap1 0x00000000 FTC Interrupt Mapping Register 1 [Memory Mapped]
    LFSMap0 0x00000000 LFS Interrupt Mapping Register 0 [Memory Mapped]
    LFSMap1 0x00000000 LFS Interrupt Mapping Register 1 [Memory Mapped]
    [100 ... 120]
    HBCMap0 0x00000000 HBC Interrupt Mapping Register 0 [Memory Mapped]
    HBCMap1 0x00000000 HBC Interrupt Mapping Register 1 [Memory Mapped]
    BTCMap0 0x00000000 BTC Interrupt Mapping Register 0 [Memory Mapped]
    BTCMap1 0x00000000 BTC Interrupt Mapping Register 1 [Memory Mapped]
    BERMap0 0x00000000 BER Interrupt Mapping Register 0 [Memory Mapped]
    BERMap1 0x00000000 BER Interrupt Mapping Register 1 [Memory Mapped]
    FTCCOffSet 0x00000000 FTC Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    LFSCOffSet 0x00000000 LFS Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    HBCCOffSet 0x00000000 HBC Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    BTCCOffSet 0x00000000 BTC Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    BERCOffSet 0x00000000 BER Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    FTCDOffSet 0x00000000 FTC Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    LFSDOffSet 0x00000000 LFS Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    HBCDOffSet 0x00000000 HBC Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    BTCDOffSet 0x00000000 BTC Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    BERDOffSet 0x00000000 BER Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    ReqPolSel1 0x00000000 Request Polarity Select Register1 [Memory Mapped]
    ReqPolSel0 0x00000000 Request Polarity Select Register0 [Memory Mapped]
    TEREvtCtrl 0x0000000A TER Event Control Register [Memory Mapped]
    TEREvtFlag 0x00000000 TER Event Flag Register [Memory Mapped]
    TEREvtOffset 0x0000003D TER Event Offset Register [Memory Mapped]

    -----------------------------

    Here are the same registers after receiving CAN messages (DCAN4).

    R Dcan4_CTL 0x0000000B 0x00121602
    R Dcan4_ES 0x0000000B 0x00000050
    R Dcan4_ERRC 0x0000000B 0x00000061
    R Dcan4_BTR 0x0000000B 0x00000707
    R Dcan4_INT 0x0000000B 0x00000000
    R Dcan4_TEST 0x0000000B 0x00000080
    R Dcan4_PERR 0x0000000B 0x00000048
    R Dcan4_REL 0x0000000B 0xA3170504
    R Dcan4_ECCDIAG 0x0000000B 0x0000000A
    R Dcan4_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan4_ECC_CS 0x0000000B 0x050A0000
    R Dcan4_ECC_SERR 0x0000000B 0x00000000
    R Dcan4_ABOTR 0x0000000B 0x047868C0
    R Dcan4_TXRQX 0x0000000B 0x00000000
    R Dcan4_TXRQ12 0x0000000B 0x00000000
    R Dcan4_TXRQ34 0x0000000B 0x00000000
    R Dcan4_TXRQ56 0x0000000B 0x00000000
    R Dcan4_TXRQ78 0x0000000B 0x00000000
    R Dcan4_NWDATX 0x0000000B 0x00000003
    R Dcan4_NWDAT12 0x0000000B 0x0000FFFF
    R Dcan4_NWDAT34 0x0000000B 0x00000000
    R Dcan4_NWDAT56 0x0000000B 0x00000000
    R Dcan4_NWDAT78 0x0000000B 0x00000000
    R Dcan4_INTPNDX 0x0000000B 0x00000000
    R Dcan4_INTPND12 0x0000000B 0x00000000
    R Dcan4_INTPND34 0x0000000B 0x00000000
    R Dcan4_INTPND56 0x0000000B 0x00000000
    R Dcan4_INTPND78 0x0000000B 0x00000000
    R Dcan4_MSGVALX 0x0000000B 0x000000FF
    R Dcan4_MSGVAL12 0x0000000B 0xFFFFFFFF
    R Dcan4_MSGVAL34 0x0000000B 0xFFFFFFFF
    R Dcan4_MSGVAL56 0x0000000B 0x00000000
    R Dcan4_MSGVAL78 0x0000000B 0x00000000
    R Dcan4_INTMUX12 0x0000000B 0x00000000
    R Dcan4_INTMUX34 0x0000000B 0x00000000
    R Dcan4_INTMUX56 0x0000000B 0x00000000
    R Dcan4_INTMUX78 0x0000000B 0x00000000
    R Dcan4_IF1CMD 0x0000000B 0x00FF0037
    R Dcan4_IF1MSK 0x0000000B 0xE0000000
    R Dcan4_IF1ARB 0x0000000B 0xE869A240
    R Dcan4_IF1MCTL 0x0000000B 0x00001088
    R Dcan4_IF1DATA 0x0000000B 0xF00A1010
    R Dcan4_IF1DATB 0x0000000B 0x0C01EF0A
    R Dcan4_IF2CMD 0x0000000B 0x00370001
    R Dcan4_IF2MSK 0x0000000B 0xE00007FF
    R Dcan4_IF2ARB 0x0000000B 0xC86B1404
    R Dcan4_IF2MCTL 0x0000000B 0x00009004
    R Dcan4_IF2DATA 0x0000000B 0x1EACAA6A
    R Dcan4_IF2DATB 0x0000000B 0x00000000
    R Dcan4_IF3OBS 0x0000000B 0x00009818
    R Dcan4_IF3MSK 0x0000000B 0xE0000000
    R Dcan4_IF3ARB 0x0000000B 0xC86B1404
    R Dcan4_IF3MCTL 0x0000000B 0x00009004
    R Dcan4_IF3DATA 0x0000000B 0x1DACAA6A
    R Dcan4_IF3DATB 0x0000000B 0x000000FF
    R Dcan4_IF3UPD12 0x0000000B 0x0000FFFF
    R Dcan4_IF3UPD34 0x0000000B 0x00000000
    R Dcan4_IF3UPD56 0x0000000B 0x00000000
    R Dcan4_IF3UPD78 0x0000000B 0x00000000
    R Dcan4_TIOC 0x0000000B 0x0004000F
    R Dcan4_RIOC 0x0000000B 0x00040009
    R Dcan3_CTL 0x0000000B 0x00001401
    R Dcan3_ES 0x0000000B 0x00000007
    R Dcan3_ERRC 0x0000000B 0x00000000
    R Dcan3_BTR 0x0000000B 0x00002301
    R Dcan3_INT 0x0000000B 0x00000000
    R Dcan3_TEST 0x0000000B 0x00000080
    R Dcan3_PERR 0x0000000B 0x00000000
    R Dcan3_REL 0x0000000B 0xA3170504
    R Dcan3_ECCDIAG 0x0000000B 0x0000000A
    R Dcan3_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan3_ECC_CS 0x0000000B 0x050A0000
    R Dcan3_ECC_SERR 0x0000000B 0x00000000
    R Dcan3_ABOTR 0x0000000B 0x00000000
    R Dcan3_TXRQX 0x0000000B 0x00000000
    R Dcan3_TXRQ12 0x0000000B 0x00000000
    R Dcan3_TXRQ34 0x0000000B 0x00000000
    R Dcan3_TXRQ56 0x0000000B 0x00000000
    R Dcan3_TXRQ78 0x0000000B 0x00000000
    R Dcan3_NWDATX 0x0000000B 0x00000000
    R Dcan3_NWDAT12 0x0000000B 0x00000000
    R Dcan3_NWDAT34 0x0000000B 0x00000000
    R Dcan3_NWDAT56 0x0000000B 0x00000000
    R Dcan3_NWDAT78 0x0000000B 0x00000000
    R Dcan3_INTPNDX 0x0000000B 0x00000000
    R Dcan3_INTPND12 0x0000000B 0x00000000
    R Dcan3_INTPND34 0x0000000B 0x00000000
    R Dcan3_INTPND56 0x0000000B 0x00000000
    R Dcan3_INTPND78 0x0000000B 0x00000000
    R Dcan3_MSGVALX 0x0000000B 0x00000000
    R Dcan3_MSGVAL12 0x0000000B 0x00000000
    R Dcan3_MSGVAL34 0x0000000B 0x00000000
    R Dcan3_MSGVAL56 0x0000000B 0x00000000
    R Dcan3_MSGVAL78 0x0000000B 0x00000000
    R Dcan3_INTMUX12 0x0000000B 0x00000000
    R Dcan3_INTMUX34 0x0000000B 0x00000000
    R Dcan3_INTMUX56 0x0000000B 0x00000000
    R Dcan3_INTMUX78 0x0000000B 0x00000000
    R Dcan3_IF1CMD 0x0000000B 0x00000001
    R Dcan3_IF1MSK 0x0000000B 0xFFFFFFFF
    R Dcan3_IF1ARB 0x0000000B 0x00000000
    R Dcan3_IF1MCTL 0x0000000B 0x00000000
    R Dcan3_IF1DATA 0x0000000B 0x00000000
    R Dcan3_IF1DATB 0x0000000B 0x00000000
    R Dcan3_IF2CMD 0x0000000B 0x00000001
    R Dcan3_IF2MSK 0x0000000B 0xFFFFFFFF
    R Dcan3_IF2ARB 0x0000000B 0x00000000
    R Dcan3_IF2MCTL 0x0000000B 0x00000000
    R Dcan3_IF2DATA 0x0000000B 0x00000000
    R Dcan3_IF2DATB 0x0000000B 0x00000000
    R Dcan3_IF3OBS 0x0000000B 0x00000000
    R Dcan3_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan3_IF3ARB 0x0000000B 0x00000000
    R Dcan3_IF3MCTL 0x0000000B 0x00000000
    R Dcan3_IF3DATA 0x0000000B 0x00000000
    R Dcan3_IF3DATB 0x0000000B 0x00000000
    R Dcan3_IF3UPD12 0x0000000B 0x00000000
    R Dcan3_IF3UPD34 0x0000000B 0x00000000
    R Dcan3_IF3UPD56 0x0000000B 0x00000000
    R Dcan3_IF3UPD78 0x0000000B 0x00000000
    R Dcan3_TIOC 0x0000000B 0x00040001
    R Dcan3_RIOC 0x0000000B 0x00040001
    R Dcan2_CTL 0x0000000B 0x00001401
    R Dcan2_ES 0x0000000B 0x00000007
    R Dcan2_ERRC 0x0000000B 0x00000000
    R Dcan2_BTR 0x0000000B 0x00002301
    R Dcan2_INT 0x0000000B 0x00000000
    R Dcan2_TEST 0x0000000B 0x00000080
    R Dcan2_PERR 0x0000000B 0x0000007A
    R Dcan2_REL 0x0000000B 0xA3170504
    R Dcan2_ECCDIAG 0x0000000B 0x0000000A
    R Dcan2_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan2_ECC_CS 0x0000000B 0x050A0000
    R Dcan2_ECC_SERR 0x0000000B 0x00000044
    R Dcan2_ABOTR 0x0000000B 0x00000000
    R Dcan2_TXRQX 0x0000000B 0x00000000
    R Dcan2_TXRQ12 0x0000000B 0x00000000
    R Dcan2_TXRQ34 0x0000000B 0x00000000
    R Dcan2_TXRQ56 0x0000000B 0x00000000
    R Dcan2_TXRQ78 0x0000000B 0x00000000
    R Dcan2_NWDATX 0x0000000B 0x00000000
    R Dcan2_NWDAT12 0x0000000B 0x00000000
    R Dcan2_NWDAT34 0x0000000B 0x00000000
    R Dcan2_NWDAT56 0x0000000B 0x00000000
    R Dcan2_NWDAT78 0x0000000B 0x00000000
    R Dcan2_INTPNDX 0x0000000B 0x00000000
    R Dcan2_INTPND12 0x0000000B 0x00000000
    R Dcan2_INTPND34 0x0000000B 0x00000000
    R Dcan2_INTPND56 0x0000000B 0x00000000
    R Dcan2_INTPND78 0x0000000B 0x00000000
    R Dcan2_MSGVALX 0x0000000B 0x00000000
    R Dcan2_MSGVAL12 0x0000000B 0x00000000
    R Dcan2_MSGVAL34 0x0000000B 0x00000000
    R Dcan2_MSGVAL56 0x0000000B 0x00000000
    R Dcan2_MSGVAL78 0x0000000B 0x00000000
    R Dcan2_INTMUX12 0x0000000B 0x00000000
    R Dcan2_INTMUX34 0x0000000B 0x00000000
    R Dcan2_INTMUX56 0x0000000B 0x00000000
    R Dcan2_INTMUX78 0x0000000B 0x00000000
    R Dcan2_IF1CMD 0x0000000B 0x00000001
    R Dcan2_IF1MSK 0x0000000B 0xFFFFFFFF
    R Dcan2_IF1ARB 0x0000000B 0x00000000
    R Dcan2_IF1MCTL 0x0000000B 0x00000000
    R Dcan2_IF1DATA 0x0000000B 0x00000000
    R Dcan2_IF1DATB 0x0000000B 0x00000000
    R Dcan2_IF2CMD 0x0000000B 0x00000001
    R Dcan2_IF2MSK 0x0000000B 0xFFFFFFFF
    R Dcan2_IF2ARB 0x0000000B 0x00000000
    R Dcan2_IF2MCTL 0x0000000B 0x00000000
    R Dcan2_IF2DATA 0x0000000B 0x00000000
    R Dcan2_IF2DATB 0x0000000B 0x00000000
    R Dcan2_IF3OBS 0x0000000B 0x00000000
    R Dcan2_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan2_IF3ARB 0x0000000B 0x00000000
    R Dcan2_IF3MCTL 0x0000000B 0x00000000
    R Dcan2_IF3DATA 0x0000000B 0x00000000
    R Dcan2_IF3DATB 0x0000000B 0x00000000
    R Dcan2_IF3UPD12 0x0000000B 0x00000000
    R Dcan2_IF3UPD34 0x0000000B 0x00000000
    R Dcan2_IF3UPD56 0x0000000B 0x00000000
    R Dcan2_IF3UPD78 0x0000000B 0x00000000
    R Dcan2_TIOC 0x0000000B 0x00040001
    R Dcan2_RIOC 0x0000000B 0x00040001
    R Dcan1_CTL 0x0000000B 0x00001401
    R Dcan1_ES 0x0000000B 0x00000007
    R Dcan1_ERRC 0x0000000B 0x00000000
    R Dcan1_BTR 0x0000000B 0x00002301
    R Dcan1_INT 0x0000000B 0x00000000
    R Dcan1_TEST 0x0000000B 0x00000080
    R Dcan1_PERR 0x0000000B 0x00000000
    R Dcan1_REL 0x0000000B 0xA3170504
    R Dcan1_ECCDIAG 0x0000000B 0x0000000A
    R Dcan1_ECCDIAG_STAT 0x0000000B 0x00000000
    R Dcan1_ECC_CS 0x0000000B 0x050A0000
    R Dcan1_ECC_SERR 0x0000000B 0x00000000
    R Dcan1_ABOTR 0x0000000B 0x00000000
    R Dcan1_TXRQX 0x0000000B 0x00000000
    R Dcan1_TXRQ12 0x0000000B 0x00000000
    R Dcan1_TXRQ34 0x0000000B 0x00000000
    R Dcan1_TXRQ56 0x0000000B 0x00000000
    R Dcan1_TXRQ78 0x0000000B 0x00000000
    R Dcan1_NWDATX 0x0000000B 0x00000000
    R Dcan1_NWDAT12 0x0000000B 0x00000000
    R Dcan1_NWDAT34 0x0000000B 0x00000000
    R Dcan1_NWDAT56 0x0000000B 0x00000000
    R Dcan1_NWDAT78 0x0000000B 0x00000000
    R Dcan1_INTPNDX 0x0000000B 0x00000000
    R Dcan1_INTPND12 0x0000000B 0x00000000
    R Dcan1_INTPND34 0x0000000B 0x00000000
    R Dcan1_INTPND56 0x0000000B 0x00000000
    R Dcan1_INTPND78 0x0000000B 0x00000000
    R Dcan1_MSGVALX 0x0000000B 0x00000000
    R Dcan1_MSGVAL12 0x0000000B 0x00000000
    R Dcan1_MSGVAL34 0x0000000B 0x00000000
    R Dcan1_MSGVAL56 0x0000000B 0x00000000
    R Dcan1_MSGVAL78 0x0000000B 0x00000000
    R Dcan1_INTMUX12 0x0000000B 0x00000000
    R Dcan1_INTMUX34 0x0000000B 0x00000000
    R Dcan1_INTMUX56 0x0000000B 0x00000000
    R Dcan1_INTMUX78 0x0000000B 0x00000000
    R Dcan1_IF1CMD 0x0000000B 0x00000001
    R Dcan1_IF1MSK 0x0000000B 0xFFFFFFFF
    R Dcan1_IF1ARB 0x0000000B 0x00000000
    R Dcan1_IF1MCTL 0x0000000B 0x00000000
    R Dcan1_IF1DATA 0x0000000B 0x00000000
    R Dcan1_IF1DATB 0x0000000B 0x00000000
    R Dcan1_IF2CMD 0x0000000B 0x00000001
    R Dcan1_IF2MSK 0x0000000B 0xFFFFFFFF
    R Dcan1_IF2ARB 0x0000000B 0x00000000
    R Dcan1_IF2MCTL 0x0000000B 0x00000000
    R Dcan1_IF2DATA 0x0000000B 0x00000000
    R Dcan1_IF2DATB 0x0000000B 0x00000000
    R Dcan1_IF3OBS 0x0000000B 0x00000000
    R Dcan1_IF3MSK 0x0000000B 0xFFFFFFFF
    R Dcan1_IF3ARB 0x0000000B 0x00000000
    R Dcan1_IF3MCTL 0x0000000B 0x00000000
    R Dcan1_IF3DATA 0x0000000B 0x00000000
    R Dcan1_IF3DATB 0x0000000B 0x00000000
    R Dcan1_IF3UPD12 0x0000000B 0x00000000
    R Dcan1_IF3UPD34 0x0000000B 0x00000000
    R Dcan1_IF3UPD56 0x0000000B 0x00000000
    R Dcan1_IF3UPD78 0x0000000B 0x00000000
    R Dcan1_TIOC 0x0000000B 0x00040001
    R Dcan1_RIOC 0x0000000B 0x00040001

    Dma
    [0 ... 99]
    GlbCtrl 0x00010300 Global Control Register [Memory Mapped]
    ChnPnd 0x00010012 Channel Pending Register [Memory Mapped]
    Stat 0x00000000 Status Register [Memory Mapped]
    HWChnEnaSet 0x0000000D H/W Channel Enable Set and Status Register [Memory Mapped]
    HWChnEnaRst 0x0000000D H/W Channel Enable Reset and Status Register [Memory Mapped]
    SWChnEnaSet 0x00000000 S/W Channel Enable Set and Status Register [Memory Mapped]
    SWChnEnaRst 0x00000000 S/W Channel Enable Reset and Status Register [Memory Mapped]
    ChnPrioSet 0x00000000 Channel Priority Set Register [Memory Mapped]
    ChnPrioRst 0x00000000 Channel Priority Reset [Memory Mapped]
    GlbChnIntEnaSet 0x0000001F Global Channel Interrupt Enable Set [Memory Mapped]
    GlbChnIntEnaRst 0x0000001F Global Channel Interrupt Enable Reset [Memory Mapped]
    ReqAssg0 0x10100415 Request Assignment Register 0 [Memory Mapped]
    ReqAssg1 0x2F050607 Request Assignment Register 1 [Memory Mapped]
    ReqAssg2 0x08090A0B Request Assignment Register 2 [Memory Mapped]
    ReqAssg3 0x0C0D0E0F Request Assignment Register 3 [Memory Mapped]
    ReqAssg4 0x10111213 Request Assignment Register 4 [Memory Mapped]
    ReqAssg5 0x14151617 Request Assignment Register 5 [Memory Mapped]
    ReqAssg6 0x18191A1B Request Assignment Register 6 [Memory Mapped]
    ReqAssg7 0x1C1D1E1F Request Assignment Register 7 [Memory Mapped]
    PrtAssg0 0x04444000 Port Assignment Register 0 [Memory Mapped]
    PrtAssg1 0x00000000 Port Assignment Register 1 [Memory Mapped]
    PrtAssg2 0x00000000 Port Assignment Register 2 [Memory Mapped]
    PrtAssg3 0x00000000 Port Assignment Register 3 [Memory Mapped]
    FTCMap 0x00000000 FTC Interrupt Mapping Register [Memory Mapped]
    LFSMap 0x00000000 LFS Interrupt Mapping Register [Memory Mapped]
    HBCMap 0x00000000 HBC Interrupt Mapping Register [Memory Mapped]
    BTCMap 0x00000000 BTC Interrupt Mapping Register [Memory Mapped]
    BERMap 0x00000000 BER Interrupt Mapping Register [Memory Mapped]
    FTCIntEnaSet 0x0000001F FTC Interrupt Enable Set [Memory Mapped]
    FTCIntEnaRst 0x0000001F FTC Interrupt Enable Reset [Memory Mapped]
    LFSIntEnaSet 0x00000000 LFS Interrupt Enable Set [Memory Mapped]
    LFSIntEnaRst 0x00000000 LFS Interrupt Enable Reset [Memory Mapped]
    HBCIntEnaSet 0x00000000 HBC Interrupt Enable Set [Memory Mapped]
    HBCIntEnaRst 0x00000000 HBC Interrupt Enable Reset [Memory Mapped]
    BTCIntEnaSet 0x00000000 BTC Interrupt Enable Set [Memory Mapped]
    BTCIntEnaRst 0x00000000 BTC Interrupt Enable Reset [Memory Mapped]
    GlbIntFlg 0x00000013 Global Interrupt Flg Register [Memory Mapped]
    FTCIntFlg 0x00000001 FTC Interrupt Flag Register [Memory Mapped]
    LFSIntFlg 0x00000013 LFS Interrupt Flag Register [Memory Mapped]
    HBCIntFlg 0x00000000 HBC Interrupt Flag Register [Memory Mapped]
    BTCIntFlg 0x00000013 BER Interrupt Flag Register [Memory Mapped]
    BERIntFlg 0x00000000 BER Interrupt Flag Register [Memory Mapped]
    FTCAOffst 0x00000001 FTCA Interrupt Channel Offset Register [Memory Mapped]
    LFSAOffst 0x00000000 LFSA Interrupt Channel Offset Register [Memory Mapped]
    HBCAOffst 0x00000000 HBCA Interrupt Channel Offset Register [Memory Mapped]
    BTCAOffst 0x00000000 BTCA Interrupt Channel Offset Register [Memory Mapped]
    BERAOffst 0x00000000 BERA Interrupt Channel Offset Register [Memory Mapped]
    FTCBOffst 0x00000000 FTCB Interrupt Channel Offset Register [Memory Mapped]
    LSFBOffst 0x00000000 LFSB Interrupt Channel Offset Register [Memory Mapped]
    HBCBOffst 0x00000000 HBCB Interrupt Channel Offset Register [Memory Mapped]
    BTCBOffst 0x00000000 BTCB Interrupt Channel Offset Register [Memory Mapped]
    BERBOffst 0x00000000 BERB Interrupt Channel Offset Register [Memory Mapped]
    PrtCtrl 0x00000000 Port Control Register [Memory Mapped]
    RamTstCtrl 0x00000000 RAM TEST Control [Memory Mapped]
    DbgCtrl 0x00000000 Debug Control [Memory Mapped]
    WpReg 0x00000000 Watchpoint Register [Memory Mapped]
    WpMsk 0x00000000 Watchpoint Mask Register [Memory Mapped]
    PrtAChnSrcAddr 0xFFF7C2B0 Port A Active Channel Source Address Register [Memory Mapped]
    PrtAChnDstAddr 0x0807F024 Port A Active Channel Destination Address Register [Memory Mapped]
    PrtAChnTrCnt 0x00000000 Port A Active Channel Transfer Count Register [Memory Mapped]
    PrtBChnSrcAddr 0xFFF7DD50 Port B Active Channel Source Address Register [Memory Mapped]
    PrtBChnDestAddr 0x0806ADF4 Port B Active Channel Destination Address Register [Memory Mapped]
    PrtBChnTrCnt 0x00000000 Port B Active Channel Transfer Count Register [Memory Mapped]
    ParCtrl 0x00000005 Parity Control Register [Memory Mapped]
    ParErrAddr 0x0000016C Parity Error Address Register [Memory Mapped]
    MpCtrl 0x00000000 Memory Protection Control Register [Memory Mapped]
    MpStat 0x00000000 Memory Protection Status Register [Memory Mapped]
    Pr0Strt 0x00000000 Start Address of region 0 [Memory Mapped]
    Pr0End 0x00000000 End Address of region 0 [Memory Mapped]
    Pr1Strt 0x00000000 Start Address of region 0 [Memory Mapped]
    Pr1End 0x00000000 End Address of region 1 [Memory Mapped]
    Pr2Strt 0x00000000 Start Address of region 2 [Memory Mapped]
    Pr2End 0x00000000 End Address of region 2 [Memory Mapped]
    Pr3Strt 0x00000000 Start Address of region 3 [Memory Mapped]
    Pr3End 0x00000000 End Address of region 3 [Memory Mapped]
    MpCtrl2 0x00000000 Memory Protection Control Register2 [Memory Mapped]
    MpStat2 0x00000000 Memory Protection Status Register2 [Memory Mapped]
    Pr4Strt 0x00000000 Start Address of region 4 [Memory Mapped]
    Pr4End 0x00000000 End Address of region 4 [Memory Mapped]
    Pr5Strt 0x00000000 Start Address of region 5 [Memory Mapped]
    Pr5End 0x00000000 End Address of region 5 [Memory Mapped]
    Pr6Strt 0x00000000 Start Address of region 6 [Memory Mapped]
    Pr6End 0x00000000 End Address of region 6 [Memory Mapped]
    Pr7Strt 0x00000000 Start Address of region 7 [Memory Mapped]
    Pr7End 0x00000000 End Address of region 7 [Memory Mapped]
    PFCtrl 0x00050000 Pattern Fill Control Register [Memory Mapped]
    UPFReg 0x00000000 Upper Pattern Fill Register [Memory Mapped]
    LPFReg 0x00000000 Lower Pattern Fill Register [Memory Mapped]
    PMCtrl 0x00050000 Pattern Mask Control Register [Memory Mapped]
    UPMReg 0x00000000 Upper Pattern Mask Register [Memory Mapped]
    LPMReg 0x00000000 Lower Pattern Mask Register [Memory Mapped]
    CullConReg 0x05000000 Cull Configuration Register [Memory Mapped]
    SEccCtrl 0x0000050A Single Bit ECC Control Register [Memory Mapped]
    SEccAddr 0x0000000C Single Bit ECC Error Address Register [Memory Mapped]
    FifoAStat 0x00000000 Fifo A Status Register [Memory Mapped]
    FifoBStat 0x00000000 Fifo B Status Register [Memory Mapped]
    FTCMap0 0x00000000 FTC Interrupt Mapping Register 0 [Memory Mapped]
    FTCMap1 0x00000000 FTC Interrupt Mapping Register 1 [Memory Mapped]
    LFSMap0 0x00000000 LFS Interrupt Mapping Register 0 [Memory Mapped]
    LFSMap1 0x00000000 LFS Interrupt Mapping Register 1 [Memory Mapped]
    [100 ... 120]
    HBCMap0 0x00000000 HBC Interrupt Mapping Register 0 [Memory Mapped]
    HBCMap1 0x00000000 HBC Interrupt Mapping Register 1 [Memory Mapped]
    BTCMap0 0x00000000 BTC Interrupt Mapping Register 0 [Memory Mapped]
    BTCMap1 0x00000000 BTC Interrupt Mapping Register 1 [Memory Mapped]
    BERMap0 0x00000000 BER Interrupt Mapping Register 0 [Memory Mapped]
    BERMap1 0x00000000 BER Interrupt Mapping Register 1 [Memory Mapped]
    FTCCOffSet 0x00000000 FTC Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    LFSCOffSet 0x00000000 LFS Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    HBCCOffSet 0x00000000 HBC Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    BTCCOffSet 0x00000000 BTC Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    BERCOffSet 0x00000000 BER Interrupt Channel Offset Register for CPU3 [Memory Mapped]
    FTCDOffSet 0x00000000 FTC Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    LFSDOffSet 0x00000000 LFS Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    HBCDOffSet 0x00000000 HBC Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    BTCDOffSet 0x00000000 BTC Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    BERDOffSet 0x00000000 BER Interrupt Channel Offset Register for CPU4 [Memory Mapped]
    ReqPolSel1 0x00000000 Request Polarity Select Register1 [Memory Mapped]
    ReqPolSel0 0x00000000 Request Polarity Select Register0 [Memory Mapped]
    TEREvtCtrl 0x0000000A TER Event Control Register [Memory Mapped]
    TEREvtFlag 0x00000000 TER Event Flag Register [Memory Mapped]
    TEREvtOffset 0x0000003D TER Event Offset Register [Memory Mapped]

    Thanks,

    Cameron

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    Got it, and I will check those registers.

  • 0 in reply to QJ Wang
    TI__Guru**** 201216 points

    DMA_CH0 or DMA_CH1 --> CAN1_IF3

    DMA_CH2 --> CAN2_IF3

    DMA_CH3 --> CAN3_IF3

    DMA_CH4 --> CAN4_IF3

    DMA channel 0/2/3 are enabled for HW triggering.

    DMA Channel 4 for CAN4_IF3 (used in your test) is not enabled for HW triggering, please double check

    Port assigned to DMA channels: DMA_CH0: 0; DMA_CH1: 4;  DMA_CH1: 2  (CAN2_IF3);  DMA_CH3(CAN3_IF3): 4;  DMA_CH4 (CAN4_IF3): 4;

    PortA destination address: 0x0807_F024 -->  buffer for DCAN data

    PortB source address: 0xFFF7_DD50 -->  DCAN1 IF3DATA. Are you using DCAN4 for your test?

     

  • 0 in reply to QJ Wang
    Prodigy 65 points

    Yes, I'm using DCAN4 for my test. Are you implying that I can only enable one port destination/source address combination at a time? In other words, would I need to enable each CAN channel's source/destination in turn for DMA to perform the read?

    Is there a problem with PrtAssg0 = 0x04444000? I wasn't sure what your comment meant.

    I notice in the register dump (attached previously) that bit 4 of the DMA HWCHENAS register is set before the data was received but afterwards it is cleared. I don't explicitly clear the bit in the software. I've tried this repeatedly in the debugger and I usually see HWCHENAS bit 4 is set (value = 0x0000001D) even after receiving CAN data, but very occasionally bit 4 gets cleared to 0 as in the above data. Either way, DMA does not successfully read the data. The code does not explicitly clear bit 4. Any ideas what could be causing this behavior? Interestingly, we are using DMA CH0 for reading ADC, and the HWCHENAS bit 0 is set at configuration of DMA for ADC but it also seems to be getting cleared somewhere. However, this does not seem to impact the operation of the ADC DMA, which is working correctly.

    One more comment: My intent is to use only DMA CH1 for DCAN1 as we are currently already using DMA CH0 for reading ADC2 data. There is a note in the MCU data sheet in the Default DMA Request Map section, "The application must ensure that only one of these DMA request sources is enabled at any time." This looks like it may be a problem since DMAREQ[16] is the request line assigned to both DCAN1 IF3 and MibADC2 G1. Is it possible to remap only the DCAN1 IF3 request to a different channel from MibADC2 G1? 

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points
    Your PrtAssg0 = 0x04444000 register configuration is perfectly correct for your intended mapping. This register assigns read/write ports to channels in 4-bit blocks:
    • 0 for DMA_CH0 (ADC, Read Port A, Write Port A)
    • 4 for DMA_CH1 (DCAN1, Read Port B, Write Port A)
    • 4 for DMA_CH2 (DCAN2, Read Port B, Write Port A)
    • 4 for DMA_CH3 (DCAN3, Read Port B, Write Port A)
    • 4 for DMA_CH4 (DCAN4, Read Port B, Write Port A)

    The clearing of the bits in HWCHENAS is a built-in behavior governed by control packet's AUTOINIT. The HWCHENAS bit is not cleared if AUTOINIT is ON, but It is cleared at the end of a block transfer if AUTOINIT is OFF.

    You are correct. The data sheet has warning that "only one of these DMA request sources is enabled at any time" means you cannot safely have both the MibADC2 G1 hardware event and the DCAN1 IF3 hardware event driving the internal logic simultaneously.

    Cameron Fruit said:
    Is it possible to remap only the DCAN1 IF3 request to a different channel from MibADC2 G1? 
    Unfortunately, you cannot shift a peripheral's hardwired DMA Request Line number. DCAN1 IF3 is permanently tied to DMAREQ[16] at the silicon layer.
    Because both DCAN1 IF3 and MibADC2 G1 share DMAREQ[16], if MibADC2 G1 fires, it will trigger whatever DMA Channel is assigned to Line 16. To make your DCAN1 IF3 DMA work, you must ensure that MibADC2 G1 DMA generation is completely disabled in your ADC configuration. Moving your ADC operations to MibADC2 G2 or Event Group completely avoids the hardware DMA conflict with DCAN1 IF3.
  • 0 in reply to QJ Wang
    Prodigy 65 points

    It appears that DMA is copying the data to the arrays now, but only when I enabled only one channel at a time in the HWCHENAR register (i.e., I needed to only enable DMA_CH4 for DMA to read the DCAN4 data, with DMA_CH0/1/2/3 all disabled). Is that the way the DMA is intended to work? 

  • 0 in reply to Cameron Fruit
    TI__Guru**** 201216 points

    Hi Cameron,

    No, that is not how the TMS570 DMA is intended to work. The DMA controller is fully designed to have multiple channels enabled simultaneously in the HWCHENAR (Hardware Channel Enable Set) register, allowing it to arbitrate and service multiple hardware triggers (like different DCAN modules or channels) concurrently based on priority.

    If enabling DMA_CH0 through DMA_CH3 completely blocks DMA_CH4 from executing, it typically indicates that one of the lower-numbered channels is continuously triggering or stuck in an active request state.
    The TMS570 DMA uses a fixed priority scheme by default, where Channel 0 has the highest priority and Channel 31 has the lowest. If DMA_CH1, DMA_CH2, or DMA_CH3 are enabled in HWCHENAR, and any of them receive a constant or un-cleared hardware request signal, the DMA hardware will repeatedly service that higher-priority channel. Because DMA_CH4 is lower priority, it will be completely starved of DMA bus cycles and will never execute its transfer.
    Please check the DREQSTAT (DMA Request Status Register). This register shows you exactly which hardware request lines are currently active.
  • 0 in reply to QJ Wang
    Prodigy 65 points

    Thanks QJ, I don't see the DREQSTAT register anywhere, but in the end my issues appear to have been solved by setting AUTOINIT ON in the channel configuration for DMA_CH4.