MSPM0G3519-Q1: Dependency of ADC linearity on the temperature

Part Number: MSPM0G3519-Q1

Hello,

Customer wants to evaluate the worst case total unadjusted error (TUE) following the datasheet section 7.12.3. As their maximum junction temperature will be 85 degC, they ask if this makes a significant difference with the datasheet figures that correspond to a temperature range up to 125 degC.

If this makes a significant difference to the TUE, could you please tell how to assess its value at 85 degC?

Thank you.


Best regards,
François.

  • Hi François,

    The ADC linearity limits in Section 7.12.3 are specified over the full recommended supply-voltage and operating-temperature range. TI does not provide a separate guaranteed INL, offset, gain-error, or TUE limit for operation only up to 85°C. Therefore, the customer should use the published maximum values when performing a guaranteed worst-case analysis, even when their maximum junction temperature is 85°C.

    For an external 3.3-V reference in 12-bit mode:

    • INL: ±2 LSB
    • Offset error: ±3.5 mV
    • Gain error: ±4 LSB
    • One LSB: 3.3 V/4096=0.806 mV

    Using the datasheet equations, TUE ≈ 6.23LSB. This corresponds to approximately 5.0 mV, or 0.152% of the 3.3-V full-scale range. The datasheet explicitly states that the maximum linearity values apply over the recommended operating range, while typical values are measured at 25°C. Operating only to 85°C may produce better actual performance, but there is no published temperature coefficient or guaranteed derating method that can be used to calculate a tighter production limit. Linear interpolation between 25°C and 125°C would not be valid. For a design requiring tighter accuracy, the customer would need to perform system-level calibration or characterize representative devices across voltage, temperature, and manufacturing lots. Any resulting 85°C limit would be customer-derived rather than a TI-guaranteed specification.

    -Brian

  • Good morning Brian!

    A point to note in the given specification is that all the errors relate to external or internal references. We are not supplying the VREF pins in the device. Does this still hold true if we use the VDD supply as the reference? 
    Another point to note is that the Gain error is specified for VRSEL = 1h. Since we are using the VDD supply as the reference, VRSEL = 0 in our case. So will there be a change in the Gain error to consider?
  • Gentle reminder on the topic