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AM2612: temperature management and example verification

David Park
Expert 7260 points

Part Number: AM2612
Other Parts Discussed in Thread: SYSCONFIG

Hi,

There are 2 questions.

Temperature management

  • In LP_AM261 evaluation board for the AM2612, but the MCU temperature reaches 55~60°C during PROFINET operation.
  • Is there any way to reduce the MCU temperature?
  • From the test, lowering the clock frequency reduced the temperature to approximately 48~50°C.

Example Verification

  • In AM2612, planning to use Core 1 for internal bus communication and Core 2 for Ethernet + PROFINET.

  • Could you expain how memory region access between CPUs works?

  • As shown below, each core (Core 1 and Core 2) has its own memory. Is it only possible to share and transfer data between these memories through the IPC (Inter-Processor Communication) function?

  • Additionally, regarding the 1.5MB memory, is it shared and accessible by all — PRU-ICSS, Core 1, and Core 2?

  • Is memory access handled in an exclusive manner? (i.e., reserved and occupied, making it inaccessible to other CPUs?)

  • Is there an example or guide available to test these features?

 

Thanks.

  • 0
    TI__Guru 60230 points

    Your observation that lowering the clock frequency reduces temperature (from 55–60°C to 48–50°C) is consistent with expected behavior, as dynamic power dissipation scales with frequency.

    Other techniques to use  

    • Peripheral Clock Gating
    • Core Frequency Scaling( which you already did)
    • Disabling PLLs (which are not used)
    • Disabling/WFI Cores (incase the core is in while loop waiting for external interrupt)
    • Power Gating of RAMs (for unused regions)

    2. Memory Region Access Between CPUs

    IPC is NOT required for data sharing. The 1.5MB On-Chip Shared RAM (OCSRAM, 3 banks × 512KB) is directly accessible by all cores — R5F Core 0, R5F Core 1, and PRU-ICSS — without needing IPC 1. Any core can directly read/write to this shared memory region. IPC mechanisms (IPC Notify, RPMessage, SafeIPC) are available for synchronization and signaling, but the data transfer itself can be done via direct memory access 2.

    Memory access is shared, NOT exclusive. Multiple cores can access the same memory region simultaneously. However, to prevent race conditions, hardware spinlocks (256 available) should be used to ensure atomic access when multiple cores read-modify-write the same data 2. Optional MPU partitioning can restrict access if needed 3.

    PRU-ICSS access: The PRU-ICSS has its own local memories (8KB DRAM per PRU, 32KB shared RAM) but can also access the global 1.5MB OCSRAM via the CBASS0 interconnect 3. Local PRU memory access is faster than global access by several cycles. For CPU-to-PRU data exchange, PRU firmware typically writes to shared memory and signals the R5F via interrupt 4.

    Key MPU configuration requirement: Shared memory regions must have isShareable=1 set in the MPU, and all cores must use identical MPU attributes for the shared region 2.

    Available SDK examples:

    • ipc_spinlock_sharedmem — demonstrates atomic shared memory access between cores using spinlocks 5
    • ipc_notify_echo and ipc_rpmsg_echo — demonstrate IPC signaling patterns 6
    • SysConfig Memory Configurator — allows marking regions as "Shared" and selecting which cores can access them 7

    Citations:

    1. AM261x Datasheet
    2. FAQ: IPC vs Shared Memory on AM26x
    3. AM261x TRM - PRU-ICSS Memory Maps
    4. E2E: AM2612 PRU-ICSS Shared Memory Communication
    5. IPC Spinlock Shared Memory Example
    6. IPC Guide - AM261x SDK
    7. Memory Configurator - AM261x SDK