Reference : Section 14.2.11.1 of TRM
Hi,
In our project, TMS570 processor is interacting with HI 6121 slave through SPI. The slave device wors as below for reading and writing.
Write :
1) Lower the chipselect, Send the write ope code, followed by data words as per the opcode. Then deactivate the chip select.
Read:
1) Lower the chipselect, Send the read ope code, followed by dummy bytes to read the number of data words as per the opcode. Then deactivate the chip select.
During entire read or write, the chip slect should be active. So for this i am setting the CSHOLD bit in the SPIDAT1 register. It is working as expected.
My slave device requires chip selective to be deactivated for 100ns in between two different opcodes.
Ex : Operation 1: CS activated, write opcode for one byte, send one byte data word, CS dectivate
Operation 2 : CS activate, write opcode for two bytes, send two bytes of data wors, CS deactivate
So during operation1 and operation2, the slave requires atleast 100ns time CS to be in deactivated state.
Is the WDELAY mentioned in the section 14.2.11.1 of TRM satisfies my requirement ? If not is there any availability in the SPI module.
