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AM263P4-Q1: VSYS_MON

Venkata Rami Reddy Vempati
Intellectual 405 points

Part Number: AM263P4-Q1

Hi Team
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  • What are the maximum and minimum voltage levels that the VSYS_MON input can withstand?
  • The specified lower threshold is 0.873 V (typical: 0.9 V, maximum: 0.927 V). What happens when the VSYS_MON voltage falls below this threshold?
  • If VSYS_MON goes below the UV threshold or above the OV threshold, does it trigger an MCU reset, generate a fault indication, or perform any other action?
  • Please provide the complete VSYS_MON fault-detection and reset flow, including the internal reset mechanism. Specifically, please explain how the UV/OV condition is detected, how the fault propagates internally, whether it generates an ESM/fault signal, and how the MCU reset is ultimately triggered.
  • Please also clarify the reset recovery mechanism



  • 0
    TI__Mastermind 40523 points
    Hi Venkata,
    The VSYS_MON pin is an external voltage monitor input that allows the AM263x device to supervise a top-level system supply voltage (e.g., a 5V rail) by comparing a scaled-down version of it against an internal 0.9V bandgap reference (±3% tolerance). It is part of the Power OK (POK) subsystem within the PMU Safety System (SAFETYSYS), which is documented in the AM263x TRM Section 6.2.2.2 (spruj17i.pdf, pg. 228) and the AM263x Datasheet Safety Comparators section (sprsp74e.pdf, pg. 73).

    1. Voltage Thresholds (C7 – System Supply Monitor)

    From the AM263x Datasheet, Section 6.8.7 Safety Comparators, comparator C7 is specifically defined as the System Supply Monitor (VSYS_MON):
    Parameter Min Typ Max Unit
    C7 – Lower Threshold (UV) 0.873 0.900 0.927 V
    A few important design notes:
    • The VSYS_MON pin is not a general-purpose I/O — it is a dedicated analog comparator input. The voltage presented at this pin is compared against the internal 0.9V bandgap reference.
    • Do not design your resistor divider to produce exactly 0.9V at the pin. Due to the ±3% comparator tolerance, doing so places your operating point inside the ambiguous region. For reliable UV detection, the nominal divider output should be above 0.927V under normal conditions and fall below 0.873V only when the system supply has truly sagged to an unacceptable level.
    • The internal comparator input has megaohm-range impedance, so the primary source of voltage error at the pin is the PCB resistor divider itself. Resistor tolerances, IR drop in traces, and current loading differences between divider configurations can all shift the measured voltage — account for this in your design margins.
    • A typical 5V system supply scaled through a 9.1kΩ / 2.4kΩ resistor divider yields a nominal VSYS_MON voltage of ~1.04V, which is a well-chosen operating point with margin above the 0.9V reference.

    2. Behavior When the Threshold Is Crossed

    The AM26x does not implement a direct Brown-Out Reset (BOR) circuit like some other MCU families (e.g., C2000/MSP). Instead, it uses a two-level voltage supervision architecture:
    Level 1 — Internal POK/VMON → ESM (Software-configurable warning):
    • The POK modules continuously monitor the VSYS_MON pin against the internal reference.
    • Monitor enable/disable is controlled via TOP_CTRL.VMON_CTRL.
    • Status can be read from TOP_CTRL.VMON_STAT.
    • The output of the voltage monitors is passed through a configurable digital glitch filter (TOP_CTRL.VMON_FILTER_CTRL.SELECT_VALUE) — from no filtering up to 14.4µs — to suppress false triggers from short transients.
    • The aggregated VMON output is forwarded to the Error Signaling Module (ESM). Individual monitor signals can be masked using TOP_CTRL.MASK_VMON_ERROR_ESM_L and TOP_CTRL.MASK_VMON_ERROR_ESM_H.
    • The ESM can be configured to generate a high-priority interrupt to the R5F cores (voltage_monitor_err_H/voltage_monitor_err_L), giving software the opportunity to take a controlled action (graceful shutdown, state save, etc.).
    Level 2 — External Voltage Supervisor → PORz / WARMRESETn (Hard reset):
    • The AM263x was designed with the expectation that an external voltage supervisor monitors the primary power rails (VDD 1.2V, VDDS33/VDDA33 3.3V) and issues a hard POR (Power-On-Reset) by asserting PORz or WARMRESETn when rails have deviated beyond recoverable levels.
    • This is explicitly noted in TRM Section 6.2.2.2 and confirmed through E2E precedent.
    • The internal POK comparators (VTRIP_POK_L typically ~0.95V on VDD_CORE) are not designed to handle catastrophic drop scenarios (e.g., VDD_CORE dropping to 0.6V) — at that point, digital logic itself may already be operating unpredictably, and the ESM-based chain cannot be guaranteed to function. An external supervisor handles this case.
    This two-level approach provides the most configurability: the internal POK/ESM layer gives early software warning, while the external supervisor provides a last-resort hardware fail-safe.

    3. Internal Fault Detection and Propagation Flow

    1. Sensing: The internal analog comparator (C7) continuously monitors the VSYS_MON pin against the 0.9V bandgap reference.
    2. Glitch Filtering: The comparator output is passed through the configurable digital glitch filter to reject spurious transitions.
    3. Flagging: A fault status bit is set in TOP_CTRL.VMON_STAT.
    4. ESM Propagation: If not masked via TOP_CTRL.MASK_VMON_ERROR_ESM_L/H, the VMON error is forwarded to the ESM as either a low- or high-priority event.
    5. Action Selection (ESM-configured):
      • Interrupt path: ESM triggers an interrupt to the R5F core(s) via the VMON error lines, allowing software to initiate a controlled response.
      • Reset path: If the system is configured to assert WARMRESETn through the ESM error output pin connected externally to the reset circuit, a warm reset can be triggered.
    6. External Supervisor (for hard faults): An external power supervisor asserting PORz initiates a full Power-On-Reset sequence, including re-latching SOP boot mode pins and executing the full boot ROM sequence.

    4. Reset Recovery

    • Power-On-Reset sequence: PORz is asserted by the external supply monitor → VDD (1.2V) and VDDS33/VDDA33 (3.3V) ramp → internal 1.8V LDO starts → once all internal monitors confirm stable supplies, SOP[3:0] pins are latched → R5F cores are unhalted and boot ROM execution begins.
    • Glitch filter debounce: The configurable glitch filter (TOP_CTRL.VMON_FILTER_CTRL) ensures the VSYS_MON fault is not re-asserted by brief noise events during recovery — the supply must remain stable for the configured filter window before the fault condition is cleared.
    • Software re-initialization: Following a reset, the firmware must re-configure the ESM and VMON modules, as register states are not preserved across a hard reset. The VMON comparator enable state (via TOP_CTRL.VMON_CTRL) should be explicitly re-initialized as part of the post-reset startup sequence.
    References:
    Best Regards,
    Zackary Fleenor
  • 0
    Intellectual 405 points

    1.What is the maximum voltage that the pin can withstand?

    2.For example, if an undervoltage (UV) or overvoltage (OV) condition occurs, is the fault asserted to the ESM, and is the resulting ESM signal then provided to the SAFETY_ERRORN pin (D4)? Is this signal flow correct..?

  • 0 in reply to Venkata Rami Reddy Vempati
    TI__Mastermind 40523 points

    Hi Venkata,

    1) The pin adheres to the Abs Max restrictions defined for the IO terminals.

    2) Only Undervolltage is monitored for the VSYS_MON comparator. Correct, the fault is asserted to the ESM, If not masked via TOP_CTRL.MASK_VMON_ERROR_ESM_L/H as either a low- or high-priority event. The action of the ESM and safety_error pin must be programmed by the application code and understood in the system reset hardware to perform the proper fault handling.

    Best Regards,

    Zackary Fleenor