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AM13E23019: AM13E230 external vref configuration

Zach O'Brien
Prodigy 31 points

Part Number: AM13E23019
Other Parts Discussed in Thread: SYSCONFIG

Hello,

I have am AM13E23019 with an external 3.0v vref attached. In Syscfg I set VREFSource to external

sysctl.VREFSource         = "DL_SYSCTL_VREF_EXTERNAL";

Which sets SOCLOCK.ANAREFCTL to DL_SYSCTL_VREF_EXTERNAL (0x001). 

But my ADC reading were about half of what they should be. This seems related to the internal divide by two used for interal 3.3v vref. From the reference manual:

When the 1.65V internal reference voltage is selected, the ADC input signal is internally divided by 2 before conversion, which effectively makes the ADC conversion range from VREFLO to 3.3V.

The reference manual also says

To enable the external reference mode, the bit ANAREFSEL in register REFCONFIGA from AnalogSubsysRegs must be set to 1 (AnalogSubsysRegs.REFCONFIGA.bit.ANAREFSEL = 1).

but then doesn't define which bit in REFCONFIGA is ANAREFSEL

image (3).png

 

I was able to resolve this by configuring both 2.5v internal and external vref, which I think disabled the internal vref connection and disables the internal divide by two.

SOCLOCK.ANAREFCTL = DL_SYSCTL_VREF_EXTERNAL | DL_SYSCTL_VREF_INTERNAL_2_5_V; (0x101)
 
But this seems like a workaround instead of the correct solution. Is this intended or does one of the reserved bits in REFCONFIGA need to be set?
  • +1
    TI__Mastermind 40523 points

    Hi Zach,

    Your "workaround" is actually the correct and intended configuration. This was a known issue in earlier SDK versions that has since been addressed.

    In SDK 26.01.00, the VREF enumerations were updated specifically to fix this behavior 1:

    • DL_SYSCTL_VREF_EXTERNAL was renamed to DL_SYSCTL_VREF_EXTERNAL_HALF_SCALE (0x001)
    • A new DL_SYSCTL_VREF_EXTERNAL_FULL_SCALE (0x101) was added
    • The SysConfig default was changed from 0x001 to 0x101

    The correct VREF modes

    Enum Value Behavior
    DL_SYSCTL_VREF_EXTERNAL_FULL_SCALE 0x101 External VREF, no ADC scaling. Apply 2.5V or 3.3V to VREFHI directly.
    DL_SYSCTL_VREF_EXTERNAL_HALF_SCALE 0x001 External VREF, ADC scales 2×. Apply 1.65V to VREFHI.
    DL_SYSCTL_VREF_INTERNAL_3_3_V 0x000 Internal 1.65V generated, ADC scales 2× (3.3V effective range).
    DL_SYSCTL_VREF_INTERNAL_2_5_V 0x100 Internal 2.5V generated, no ADC scaling.
    2

    What you should do

    For your 3.0V external VREF, use: DL_SYSCTL_setVREF(DL_SYSCTL_VREF_EXTERNAL_FULL_SCALE); This writes 0x101 to ANAREFCTL — exactly what your "workaround" does. Bit 8 (ANAREF2P5SEL) disables the internal divide-by-2 scaling, and bit 0 (ANAREFSEL) selects external reference mode 3.

    Regarding REFCONFIGA / ANAREFSEL

    The TRM references AnalogSubsysRegs.REFCONFIGA.bit.ANAREFSEL but the actual register is ANAREFCTL with ANAREFSEL at bit 0 3. The TRM also explicitly states: do not configure the voltage reference mode by directly writing to the ANAREFCTL register — use DL_SYSCTL_setVREF() instead, as it ensures correct trim values are loaded 4.

    Summary

    Update your SDK to 26.01.00 or later and use DL_SYSCTL_VREF_EXTERNAL_FULL_SCALE in SysConfig. Your value of 0x101 is correct!

    1. Release Notes 26.01.00
    2. DL_SYSCTL VREF_MODE API Reference
    3. AM13E230x TRM — ANAREFCTL Register
    4. AM13E230x TRM — Selecting Reference Mode

    Best Regards,

    Zackary Fleenor