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AM263P4-Q1: SIP memory

Venkata Rami Reddy Vempati
Intellectual 405 points

Part Number: AM263P4-Q1
Other Parts Discussed in Thread: AM263P4, SYSCONFIG, , UNIFLASH

Regarding the AM263P4 F-package SIP with 8 MB memory, could you please provide an example code demonstrating how to access the 8 MB memory and read the manufacturer ID and device ID for the SIP package and also to store the data in sip memory 

  • 0
    TI__Expert 3600 points

    Hi Venkata,
    There are some example in AM263Px MC+SDK.
    Please refer to below examples

    C:\ti\mcu_plus_sdk_am263px_26_00_00_06\examples\drivers\ospi\ospi_flash_diag
    Identifies the flash chip and reads its specifications

    C:\ti\mcu_plus_sdk_am263px_26_00_00_06\examples\drivers\ospi\ospi_flash_io
    Tests basic flash read/write/erase operations

    Note that while using these examples, before building make sure to migrate them to the AM263px variant you are using from sysconfig.


    Note -
    If you are using AM263P4-Q1, you won't fine ZCZ-F (SIP) Package option, this is known bug and will be corrected in next release.
    To choose ZCZ-F package select AM263P4.

  • 0 in reply to Lakshya Verma
    Intellectual 405 points

    C:\ti\mcu_plus_sdk_am263px_26_00_00_06\examples\drivers\ospi\ospi_flash_io
    Tests basic flash read/write/erase operations

    I'm facing an issue:
    unable to read, write, or erase the memory

    Cortex_R5_0: ERROR: Board_flashOpen:292: FLASH open failed for instance 0 !!!

    Cortex_R5_0: ASSERT: 0.7864s: ../ospi_flash_io.c:ospi_flash_io_main:64: status==SystemP_SUCCESS failed !!!


    C:\ti\mcu_plus_sdk_am263px_26_00_00_06\examples\drivers\ospi\ospi_flash_diag
    Identifies the flash chip and reads its specifications
    Yes,i got it.

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Starting ...

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Flash Manufacturer ID : 0x9D

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Flash Device ID       : 0x5A17

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Executing Flash Erase on first block...

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Done !!!

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Performing Write-Read Test...

    Cortex_R5_0: [OSPI Flash Diagnostic Test] Write-Read Test Passed!

    Cortex_R5_0: [QSPI Flash Diagnostic Test] SFDP Information :

    Cortex_R5_0: ================================================

    Cortex_R5_0:                       SFDP                     

    Cortex_R5_0: ================================================

    Cortex_R5_0: SFDP Major Revision                       : 0x1

    Cortex_R5_0: SFDP Minor Revision                       : 0x9

    Cortex_R5_0: Number of Parameter Headers in this Table : 4

    Cortex_R5_0:

    Cortex_R5_0: Types of Additional Parameter Tables in this flash

    Cortex_R5_0: ---------------------------------------------------

    Cortex_R5_0: 4 BYTE ADDRESSING MODE INSTRUCTIONS TABLE

    Cortex_R5_0: NOR SPI PROFILE TABLE

    Cortex_R5_0: OCTAL DDR MODE COMMAND SEQUENCE TABLE

    Cortex_R5_0:

    Cortex_R5_0: Parsing of OCTAL DDR MODE COMMAND SEQUENCE TABLE table not yet supported.

    Cortex_R5_0: JSON Data for the flash :

    Cortex_R5_0:

    Cortex_R5_0: {

    Cortex_R5_0:

    Cortex_R5_0:    "flashSize": 8388608,

    Cortex_R5_0:    "flashPageSize": 256,

    Cortex_R5_0:    "flashManfId": "0x9D",

    Cortex_R5_0:    "flashDeviceId": "0x5A17",

    Cortex_R5_0:    "flashBlockSize": 131072,

    Cortex_R5_0:    "flashSectorSize": 4096,

    Cortex_R5_0:    "cmdBlockErase3B": "0xD8",

    Cortex_R5_0:    "cmdBlockErase4B": "0xDC",

    Cortex_R5_0:    "cmdSectorErase3B": "0x20",

    Cortex_R5_0:    "cmdSectorErase4B": "0x21",

    Cortex_R5_0:    "protos": {

    Cortex_R5_0:            "p111": {

    Cortex_R5_0:                    "isDtr": false,

    Cortex_R5_0:                    "cmdRd": "0x03",

    Cortex_R5_0:                    "cmdWr": "0x02",

    Cortex_R5_0:                    "modeClksCmd": 0,

    Cortex_R5_0:                    "modeClksRd": 0,

    Cortex_R5_0:                    "dummyClksCmd": 0,

    Cortex_R5_0:                    "dummyClksRd": 0,

    Cortex_R5_0:                    "enableType": "0",

    Cortex_R5_0:                    "enableSeq": "0x00",

    Cortex_R5_0:                    "dummyCfg": null,

    Cortex_R5_0:                    "protoCfg": null,

    Cortex_R5_0:                    "strDtrCfg": null

    Cortex_R5_0:            },

    Cortex_R5_0:            "p112": null,

    Cortex_R5_0:            "p114": null,

    Cortex_R5_0:            "p118": {

    Cortex_R5_0:                    "isDtr": false,

    Cortex_R5_0:                    "cmdRd": "0x7C",

    Cortex_R5_0:                    "cmdWr": "0x84",

    Cortex_R5_0:                    "modeClksCmd": 0,

    Cortex_R5_0:                    "modeClksRd": 1,

    Cortex_R5_0:                    "dummyClksCmd": 0,

    Cortex_R5_0:                    "dummyClksRd": 7,

    Cortex_R5_0:                    "enableType": "0",

    Cortex_R5_0:                    "enableSeq": "0x00",

    Cortex_R5_0:                    "dummyCfg": null,

    Cortex_R5_0:                    "protoCfg": null,

    Cortex_R5_0:                    "strDtrCfg": null

    Cortex_R5_0:            },

    Cortex_R5_0:            "p444s": null,

    Cortex_R5_0:            "p444d": null,

    Cortex_R5_0:            "p888s": null,

    Cortex_R5_0:            "p888d": {

    Cortex_R5_0:                    "isDtr": false,

    Cortex_R5_0:                    "cmdRd": "0x0B",

    Cortex_R5_0:                    "cmdWr": "0x12",

    Cortex_R5_0:                    "modeClksCmd": 0,

    Cortex_R5_0:                    "modeClksRd": 0,

    Cortex_R5_0:                    "dummyClksCmd": 8,

    Cortex_R5_0:                    "dummyClksRd": 14,

    Cortex_R5_0:                    "enableType": "0",

    Cortex_R5_0:                    "enableSeq": "0x00",

    Cortex_R5_0:                    "dummyCfg": {

    Cortex_R5_0:                            "isAddrReg": false,

    Cortex_R5_0:                            "cmdRegRd":"0x00",

    Cortex_R5_0:                            "cmdRegWr":"0x00",

    Cortex_R5_0:                            "cfgReg":"0x00000000",

    Cortex_R5_0:                            "shift":0,

    Cortex_R5_0:                            "mask":"0x00",

    Cortex_R5_0:                            "bitP":14

    Cortex_R5_0:                    },

    Cortex_R5_0:                    "protoCfg": {

    Cortex_R5_0:                            "isAddrReg": false,

    Cortex_R5_0:                            "cmdRegRd": "0x00",

    Cortex_R5_0:                            "cmdRegWr": "0x00",

    Cortex_R5_0:                            "cfgReg": "0x00000000",

    Cortex_R5_0:                            "shift": 0,

    Cortex_R5_0:                            "mask": "0x00",

    Cortex_R5_0:                            "bitP": 0

    Cortex_R5_0:                    },

    Cortex_R5_0:                    "strDtrCfg": {

    Cortex_R5_0:                            "isAddrReg": false,

    Cortex_R5_0:                            "cmdRegRd": "0x00",

    Cortex_R5_0:                            "cmdRegWr": "0x00",

    Cortex_R5_0:                            "cfgReg": "0x00000000",

    Cortex_R5_0:                            "shift": 0,

    Cortex_R5_0:                            "mask": "0x00",

    Cortex_R5_0:                            "bitP": 0

    Cortex_R5_0:                    }

    Cortex_R5_0:            },

    Cortex_R5_0:            "pCustom": {

    Cortex_R5_0:                    "fxn": null

    Cortex_R5_0:            }

    Cortex_R5_0:    },

    Cortex_R5_0:    "addrByteSupport": "1",

    Cortex_R5_0:    "fourByteAddrEnSeq": "0xA1",

    Cortex_R5_0:    "cmdExtType": "REPEAT",

    Cortex_R5_0:    "resetType": "0x30",

    Cortex_R5_0:    "deviceBusyType": "0",

    Cortex_R5_0:    "cmdWren": "0x06",

    Cortex_R5_0:    "cmdRdsr": "0x05",

    Cortex_R5_0:    "srWip":  0,

    Cortex_R5_0:    "srWel":  1,

    Cortex_R5_0:    "cmdChipErase": "0xC7",

    Cortex_R5_0:    "rdIdSettings": {

    Cortex_R5_0:            "cmd": "0x9F",

    Cortex_R5_0:            "numBytes": 5,

    Cortex_R5_0:            "dummy4": 0,

    Cortex_R5_0:            "dummy8": 0

    Cortex_R5_0:    },

    Cortex_R5_0:    "xspiWipRdCmd": "0x00",

    Cortex_R5_0:    "xspiWipReg": "0x00000000",

    Cortex_R5_0:    "xspiWipBit": 0,

    Cortex_R5_0:    "flashDeviceBusyTimeout": 20000000,

    Cortex_R5_0:    "flashPageProgTimeout": 120

    Cortex_R5_0: }

    Cortex_R5_0:

    Cortex_R5_0: All tests have passed!!



  • 0 in reply to Venkata Rami Reddy Vempati
    TI__Expert 3600 points

    Hi Venkat,
    I imported this project
    C:\ti\mcu_plus_sdk_am263px_26_00_00_06\examples\drivers\ospi\ospi_flash_io\am263px-cc

    and then performed the migration step which i just mentioned above and all the test cases were passed.

    Did you use lp one ?


     

  • 0 in reply to Lakshya Verma
    TI__Expert 3600 points

    For your reference, also check.

    AM263Px MCU+ SDK: Migrating examples from package to package in AM263PX

    Our SDK also provides a script to migrate examples.

  • 0 in reply to Lakshya Verma
    Intellectual 405 points

    Hi Laksya,

    We have also successfully passed the test cases. Could you please explain the next steps for flashing our application code on the custom board (AM263P4 F-package SiP with 8 MB memory)? Specifically, I would appreciate a detailed procedure for programming the device using the UniFlash tool, including the required boot mode configuration and the complete booting process.
            pls explain the one GPIO/Hello world example
    Please give us the proper procedure at the earliest.
  • 0 in reply to Venkata Rami Reddy Vempati
    TI__Expert 3600 points



    1) Import your application example (e.g. hello world) and sbl application example (e.g. sbl_ospi_multicore_elf in SDK ) in CCS.
    2) Build both examples. Open Uniflash , start a new session.
    3) Upload 3 files (tiimage file of sbl application  and mcelf , mcelf_xip files of the main application) on uniflash just like below image.


    4) Put your board in OSPI boot mode (for this demonstration)
    5) Load Images
    6) Power cycle your device and open the UART com port to see the logs.