Part Number: AM6442
Hello,
I am comparing the sequential write performance of Cacheable WBWA and Normal Non-cacheable MSRAM regions on the AM6442 Cortex-R5F.
I use two separate 16 KB buffers with the following MPU configurations:
- Cacheable: Normal Memory, Write-Back + Write-Allocate, Non-shareable
- Non-cacheable: Normal Memory, Non-cacheable, Non-shareable
For the cacheable test, I invalidate the region before starting the measurement so that the test begins with cold cache lines.
Here is the code of mine:
The results are highly repeatable:
Non-cacheable + DSB : ~311,000–312,000 cycles
So for this particular 16 KB sequential write workload, the cacheable configuration is approximately 3% slower.
I expected the cacheable WBWA configuration to provide better sequential write performance, but the measured results do not confirm this expectation. In this test, the cacheable path is slightly slower once the required cache write-back and completion barrier are included.
My questions are:
- Is this result expected for AM6442 Cortex-R5F writing sequentially to MSRAM?
- Is Cache_wb() + DSB versus Normal Non-cacheable write + DSB a reasonable comparison when I want both measurements to include the cost of making the written data reach the underlying memory?
- Could the similar performance be explained by the Cortex-R5 store buffer combining sequential Normal Non-cacheable writes before issuing AXI transactions?
- Is there any TI benchmark comparing Cortex-R5F sequential write performance for WBWA cacheable memory including write-back cost against Normal Non-cacheable memory?
I also verified the linker map and MPU configuration: the 16 KB cacheable buffer is placed at 0x70100000 inside a 64 KB Normal Write-Back Write-Allocate region, while the 16 KB non-cacheable buffer is placed at 0x70110000 inside a separate 64 KB Normal Non-cacheable region. These higher-priority MPU regions correctly override the general 2 MB MSRAM region covering 0x70000000–0x701FFFFF.
