Part Number: AM2612
Other Parts Discussed in Thread: LP-AM261
Our customer want to use a PSRAM with OSPI1 of AM261x.
Can OSPI1 tolerate the variable latency output data during a read operation?
For example, in APS12808L-OBMX-BA used on LP-AM261, the delay from the read pre-amble to the beginning of valid data (the 1st DQS/DM rising edge) can vary anywhere between LC to LC×2 in latency cycle. Alternatively, the delay can be fixed at the worst-case value of LC×2 instead of varying.
APS12808L-OBMx OPI Xccela PSRAM
https://www.apmemory.com/tw/downloadFiles/032411222116600644
8.5 Read Operation (Page 12)
When using DQS clocking topologies for OSPI, the OSPI uses the DQS output from the attached device as the PHY receive data capture clock and samples the incoming data into a FIFO. Therefore, it appears that the variable latency output dat can be tolerated.
Best regards,
Daisuke
