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AM2612: Using PSRAM with OSPI1

Daisuke Maeda
Guru 20465 points

Part Number: AM2612
Other Parts Discussed in Thread: LP-AM261

Our customer want to use a PSRAM with OSPI1 of AM261x.

Can OSPI1 tolerate the variable latency output data during a read operation?

For example, in APS12808L-OBMX-BA used on LP-AM261, the delay from the read pre-amble to the beginning of valid data (the 1st DQS/DM rising edge) can vary anywhere between LC to LC×2 in latency cycle. Alternatively, the delay can be fixed at the worst-case value of LC×2 instead of varying.

APS12808L-OBMx OPI Xccela PSRAM
https://www.apmemory.com/tw/downloadFiles/032411222116600644
8.5 Read Operation (Page 12)

When using DQS clocking topologies for OSPI, the OSPI uses the DQS output from the attached device as the PHY receive data capture clock and samples the incoming data into a FIFO. Therefore, it appears that the variable latency output dat can be tolerated.

Best regards,

Daisuke

 

  • 0
    TI__Expert 3560 points

    Hi Daisuke,
    Let me check I will get back to you

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke,
    Our OSPI IP support variable latency, but you have to retune things.
    Currently it is not supported in our SDK driver.

    I advise preferring fixed latency


  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Lakshya Verma said:
    Our OSPI IP support variable latency, but you have to retune things.

    What things are retuned?

    According to the description below in the TRM, when configured to use DQS as a clock, it appears that the only condition for sampling the incoming data into a FIFO is DQS. If so, sampling should begin on the 1st DQS rising edge regardless of any changes in latency. Therefore, it should support both fixed latency and variable latency without any configuration changes.

    13.3.4.2.5.4.2.1.4 External Pull Down on DQS
    "When configured to use DQS, the controller uses the DQS as a clock, which samples the incoming data into a FIFO. Noise on the DQS when it is HiZ can cause spurious false triggering of the FIFO and filling it with invalid data. There is no way to clear this data except to reset the OSPI module."

    Is my understanding incorrect?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Maeda-san,

    Below is the response from our hardware testing team.

    "mostly all the parameters. go back to master mode, check for master lock for half cycles. perform tuning for RD data capture, tx_dll, rx_dll".

    This variable latency feature is only tested for experimentation purpose only and our current SDK driver doesn't support it yet.

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Your hardware testing team mentions DLL. The DLL delays the sampling clock or DQS signal to align it with the center of the data valid window.

    The latency for the PSRAM is the delay from the read pre-amble to the beginning of valid data (the 1st DQS/DM rising edge), not the delay between the data and DQS. The data and DQS should be output from the PSRAM almost simultaneously regardless of any changes in latency.

    Please review the PSRAM (APS12808L-OBMx) datasheet again.

    APS12808L-OBMx OPI Xccela PSRAM
    www.apmemory.com/.../032411222116600644
    8.5 Read Operation (Page 12)

    Best regards,

    Daisuke

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    The Read DQS/DM & DQ timing for PSRAM is as shown below. The timing is the same for both fixed latency and variable latency.

    APS12808L-OBMx OPI Xccela PSRAM
    www.apmemory.com/.../032411222116600644
    Figure 9: Read DQS/DM & DQ timing (Page 14)
    Table 28: DDR timing parameters (Page 29)

    I understand that the OSPI can support both fixed latency and variable latency without any configuration changes.

    Is my understanding incorrect?

    Best regards,

    Daisuke

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    I apologize for posting repeatedly.

    If the variable latency is used, can the PHY tuning algorithm operate incorrectly?

    OSPI Phy Tuning Algorithm
    software-dl.ti.com/.../DRIVERS_OSPI_HLD_PAGE.html
    software-dl.ti.com/.../DRIVERS_OSPI_LLD_PAGE.html

    Can the application note for Sitara processors shown below be applied to AM261x?

    Enhanced OSPI PHY Tuning Algorithm for SitaraTM Processors on MCU+ SDK
    www.ti.com/.../sdaa315.pdf

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke-san,
    Let me discuss this with our HW expert and get back to you.

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your support. Our customer is waiting for your reply.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke San,

    If the variable latency is used, can the PHY tuning algorithm operate incorrectly?
    This haven't been tested yet.

    Can the application note for Sitara processors shown below be applied to AM261x?
    Yes

    May I know, why customer wants to use variable read latency?
    It would impact only the first read and ranging from 5 to 10 cycles if the Variable read. So, the impact should be negligible even if enabled. 

    Best Regards,
    Lakshya Verma

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Lakshya Verma said:
    May I know, why customer wants to use variable read latency?

    Our customer expects to perform frequent byte- and word-sized read/write operations and wants to minimize the duration of each access as much as possible.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Daisuke-san,
    In APS PSRAM byte (8bit) writes are note supports.
    We may add the variable latency support in the next SDK release.

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Lakshya Verma said:
    In APS PSRAM byte (8bit) writes are note supports.

    I understand that OSPIx_DQS is input only and is never driven as an output by the controller.

    Our customer has checked the thread below and finds it hard to believe that OSPIx_DQS does not work as data mask,and suspects that this may be a defect.

    e2e.ti.com/.../am261-som-evm-am261x-required-sysconfig-and-ospi-register-settings-for-octal-ddr-psram-with-phy-mode-enabled

    AM261x OSPI does NOT comply with JESD251 (xSPI), correct?

    In JESD251D Profile 2.0 8D-8D-8D, the Data Strobe (DS) is used as data mask for write data.

    To write byte-sized data, is a word-sized Read-Modify-Write operation required, similar to register access?

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke-san,
    Yes, AM261x OSPI doesn't support JESD251 (xSPI)

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    To write a byte-sized data in a memory mapped direct mode, is a word-sized Read-Modify-Write operation required, similar to register access?

    Best regards,

    Daisuke

  • 0 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke-san,
    APS Memory on AM261x LP doesn't support single byte writes 

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Is the memory-mapped region (OSPI1_DATA: 0xA000_0000 - 0xA7FF_FFFF) for OSPI1 in memory mapped direct mode accessible by R5F core through caches (ICACHE/DCACHE)?

    Our customer want to use the PSRAM connected to OSPI1 in the same way as internal SRAM.

    Since accesses through the caches are performed in cache line-sized units, byte-sized accesses by R5F core should also be possible.

    Best regards,

    Daisuke

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    Please give me an answer as soon as possible. Your prompt reply would be appreciated.

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke-san,

     The OSPI1 memory-mapped region (0xA000_0000 onward) is accessible by the R5F, and catchability is set per region in the MPU.

    Data read/write: write operations are not performed unless the region is configured as strongly ordered, so we use strongly ordered by default. Reads work with the region either cached or strongly ordered. If you need cached reads, you can change the MPU configuration to cached at runtime before the read. Invalidate the cache for that range first so no stale lines are read. But generally, cache is not used ,

    Execute in place (XIP): the region is cached in this mode.

    Regards,
    Lakshya Verma

  • 0 in reply to Lakshya Verma
    Guru 20465 points

    Hi Lakshya-san,

    Thank you for your reply.

    I understand that the OSPI1 memory-mapped region cannot be configured as cacheable for write operations.

    Is it correct that write operations to the OSPI1 memory-mapped region configured as strongly ordered are supported?

    In the TRM, the memory mapped direct mode is described with the functionality shown below, which appears to indicate that only read operations are supported.

    AM261x Sitara Microcontrollers Technical Reference Manual (Rev. B)

    1.4.13 Octal Serial Peripheral Interface (OSPI) - Page 24
    "Memory mapped direct mode of operation for flash data transfer and XIP from flash"

    13.3.4.2.5.1.1 OSPI Features - Page 1574
    "Memory mapped direct mode of operation for performing flash data transfers and executing code from flash memory."

    Best regards,

    Daisuke

  • +1 in reply to Daisuke Maeda
    TI__Expert 3560 points

    Hi Daisuke-san,
    Yes, that's correct. Write operations to the OSPI1 memory-mapped region are supported when the region is configured as strongly ordered in the MPU. Writes are not performed when the region is configured as cacheable, so cached writes are not supported. Reads work with the region either cached or strongly ordered.