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Original question:

AM2434: AM2434

AM2434: DP83869HMRGZR PHY address

Shashank B C
Prodigy 10 points

Part Number: AM2434
Other Parts Discussed in Thread: LP-AM243, DP83869, TMDS243EVM, TMDS64EVM

We have developed custom board using AM2434BSFFHIALXR  and DP83869HMRGZR PHY for Ethernet-IP application , schematic is same as Eval-kit LP-AM2434 , but one PHY is working and one more PHY is not alive. verified clock and reset of both the PHY.  we are getting following output.



image (8).png

  • 0
    TI__Genius 15000 points

    Hello Shashank,

    Thank you for your query !

    From the reused schematic of the LP-AM243 EVM (SPRR433D.ZIP available at https://www.ti.com/tool/LP-AM243)  I  understand that you have attached two DP83869 Ethernet PHYs to the two RGMII ports of the  PRU-ICSS1 GeMAC controller -> PRG1_RGMII1 and PRG1_RGMII2 respectively. I am referring to the latest LP-AM243 schematic revision PROC109_E3. You have the MDIO ports of the two DP83869 PHYs attached to the same PRU-ICSS1 GeMAC controller MDIO bus.

     Q1. Have you populated the TS3DDR3812RUAR multiplexer on your board ? If yes, is there a chance that you enabled the RX/TX connections from the  PHY0 (not OK) to the CPSW3g CPSW_RGMII1 port instead of to the PRU_ICSS1 GeMAC PRG1_RGMII1. Could you please check ?

    Q2. Is it possible that you used invalid bootstrapping resistor combination to select the PHY address (reported as 0 in the log). PHY address assignment to 0x0 on MDIO bus is not recommended (although permissible by Clause 22). Please try to use 0x3, updating the bootstrap address configuration as shown in the the Figure,  AM64x/AM243x Ethernet Interfaces - ICSSG1 Ethernet Strap Settings of the Section, Ethernet Interface / Section, DP83869 PHY Default Configuration / document: https://www.ti.com/lit/ug/spruj63d/spruj63d.pdf#page=42  - EVM User's Guide: TMDS243EVM TMDS64EVM AM64x/AM243x Evaluation Module.

    Q3. There is an Advisory Note i2329 in the AM64x/AM243x Silicon Errata  (valid for your AM2434BSFFHIALXR silicon revision 2.0 processor).

    If A1 and A2 show that your configuration is OK, are you sure that the i2329 workaround is applied in the PRU-ICSS GeMAC controller MDIO driver.

    For the PRU-ICSSG it shall be done as follows:

    I hope this helps find the issue with PHY0.

    Thank you !

    Best Regards,

    Anastas Yordanov

  • 0 in reply to Anastas Yordanov
    TI__Guru**** 232585 points

    Hello Shashank,

    Did you try changing the address or swapping the address for the 2 EPHYs and perform some tests.

    Can you please share the schematic over private chat to review.

    Some of the likely causes could be EPHY related or the MDIO interface related.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    Prodigy 10 points

    HI,

    I tried changing the strap resistor. But same result.

  • 0 in reply to Shashank B C
    TI__Guru**** 232585 points

    Hello Shashank,

    Please elaborate the observations.

    It may be likely the PHY is not function. Please check if the link works.

    Regards,

    Sreenivasa

  • 0 in reply to Kallikuppa Sreenivasa
    TI__Genius 15000 points

    Hello Shashank,

    Can you shortly confirm that :

    Q1- no multiplexer is populated on your board, or if populated, the multiplexer setting is ok.

    Q2 - you tried to change the PHY0 address with the correct bootstrap resistors from 0x0 to 0x3.

    Q3 - The i2329 workaround per PRU-ICCSG Ethernet MAC controller. MDIO port is applied. 

    Thank you in advance !

    Best Regards,

    Anastas