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AM263P4: R5F BRTCM Interleaving

Ilan Messing
Prodigy 40 points

Part Number: AM263P4

Arm® manuals document that it is left to the processor implementation the memory interleaving pattern of BTCM. IIRC it can either be the MSB address bit or bit 3. How is it implemented on the AM263Px family?

As a follow up, is it possible for peripheral-to-BTCM DMA transfer? for example SPI DMA to AND from BTCM, or eCAP edges being transferred to BTCM

Thank you for your assistance!