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AM263P4-Q1: AM263PX-MCAL-SDK: PBIST Positive Test

Vandana Chintala
Prodigy 70 points

Part Number: AM263P4-Q1

Hi Team,
Could you please provide some info on what are these memory regions CR5A ROM0 and ROM1? We are planning to do PBIST Test as part of SBL, we are using R5FSS0- Core 0 in lockstep mode. In this context, are we needed to test memory regions 16 and 17? Can you also provide insight on memory regions 48-51, Since we are using core 0 only 48 needs to be tested as part of PBIST test or both 48 and 49 are required. 

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Thanks & Regards, 
Vandana Chintala 

  • 0
    TI__Guru* 80376 points

    Hi Vandhana,

    I am checking this issue now and will provide you an update as soon as possible.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru* 80376 points

    Hi Vandhana,

    Vandana Chintala said:
    Could you please provide some info on what are these memory regions CR5A ROM0 and ROM1?

    The CR5A ROM refers to the Boot ROM embedded within the CR5A subsystem (which is the MSS — Main SubSystem).

    • MEM_CR5A_ROM0 (Region 16): First bank/partition of the CR5A Boot ROM.
    • MEM_CR5A_ROM1 (Region 17): Second bank/partition of the CR5A Boot ROM.
    Vandana Chintala said:
    We are planning to do PBIST Test as part of SBL, we are using R5FSS0- Core 0 in lockstep mode. In this context, are we needed to test memory regions 16 and 17?

    Yes, it is recommended to test these regions.

    Regions 16 and 17 both should be tested as part of your SBL PBIST sequence.

    Vandana Chintala said:
    Can you also provide insight on memory regions 48-51,

    These regions correspond to the TCM (Tightly Coupled Memory) or cache memories local to each R5F core.

    Vandana Chintala said:
    Since we are using core 0 only 48 needs to be tested as part of PBIST test or both 48 and 49 are required. 

    In R5FSS0 Lockstep Mode, you MUST test BOTH Region 48 AND Region 49.

    • In lockstep mode, Core 0 and Core 1 of R5FSS0 execute identical instructions simultaneously. Core 1 acts as the shadow/checker core.
    • Even though Core 1 is not independently programmable by the user, its local memory (TCM/cache) is still physically present and active.

    So, we should perform test for both regions 48 and 49.

    --
    Thanks & regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Prodigy 70 points

    Hi Jagadish,

    Thanks for the info. So in this context, If we are planning to test regions corresponding to TCM (regions mentioned below)...In TCMA address 0x0, we have vector table residing. Since PBIST is destructive test, Is it possible to move the vector table to some other location and update some register to indicate that moved location; then test TCMA and then move it back.



    Thanks & regards, 
    Vandana

  • 0 in reply to Vandana Chintala
    TI__Guru* 80376 points

    Hi Vandana,

    As mentioned in this user guide,

    User Guide

    PBISTROM, MEM_MSS_L2_0, MEM_MSS_L2_1, ATCM0_R5SS0, ATCM0_R5SS1, BTCM0_R5SS0 and BTCM0_R5SS1 are already taken care by ROM PBIST. So, no need to test these memories again at SBL. 

    PBIST at boot can detect permanent faults and ECC SECDED in run time to detect latent faults. For remaining memories, we always suggest customer to perform PBIST at very beginning of the SBL as this test is destructive in nature.

    --
    Thanks & Regards,
    Jagadish.