I would like to turn off the clock to peripherals that are not being used to reduce power. However, all examples I found enable clocks for everthing and I can not find any documentation of the bits in the PSPPWRDWNCLR[0-3] regesters. It talks about one bit for each quadrant. but no where does it show which peripheral/quadrent mapping.
Thanks,
John
John,
In the TRM for TMS570LS3137ZWT the PSPWRDWNSET0 register is defined as following:
Here is the way this register is implemented.
The quadrant definition is done as following:
Back in the TRM, in the memory map section, the following table describes which peripheral select is used to select each peripheral module.
A peripheral select as a 1kb size. Depending on the module, the full, half or quarter of a peripheral select can be used.
So we have 4 quadrant for each peripheral select.
As example, let see PS2. This peripheral select decodes the all addresses between 0xFFF7_F400 and 0xFFF7_F700.
MIBSPI1 and SPI2 are mapped to this PS2 as following:
PS2 Quadrant 0 and quadrant 1 for MIBSPI1for a total of 512 bytes.
PS2 Quadrant 2 and quadrant 3 for SPI2 for a total of 512 bytes.
This definition applies for:
Peripheral Protection Set Register 0, 1, 2, 3
Peripheral Protection Clear Register 0, 1, 2, 3
Peripheral Power-Down Set Register 0, 1, 2, 3
Peripheral Power-Down Clear Register 0, 1, 2, 3
In addition to this peripheral clock management, the TMS570LS3137ZWT has multiple power domain.PD1 to PD5.
Power Domain can be switched on and off (via PMM Module) to reduce power consumption. (PD1 is an always on domain)
When a power domain is off, all module/ressources cannot be used anymore.
Please refer to the Data Sheet and TRM for additional information.
Thanks and Regards,
Jean-Marc
