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AM263P4-Q1: How to Improve XIP Execution Performance

makoto yamashita
Prodigy 90 points

Part Number: AM263P4-Q1
Other Parts Discussed in Thread: SYSCONFIG

■Configuration
- AM263Px MCU+ SDK: 11.00.00.19
- CCS: 20.3.0.00014
- FLASH: IS25LX128

■Sysconfig OSPI Settings

image.png

■Evaluation Details
We placed part of the program in the XIP region and compared its execution speed with that of OCRAM execution.
The following samples were used as reference for this evaluation:
examples\benchmarks\optiflash_benchmark\flash_xip
examples\benchmarks\optiflash_benchmark\ocram
As a result of the comparison, the XIP execution speed was approximately 2.5 to 5.6 times slower than OCRAM execution.

■Attempts to Improve Speed
Attempt 1: Enabling PHY Mode
We enabled "PHY Mode" in SysConfig, but there was no change in execution speed.

Attempt 2: Executing OSPI_phyTuneDDR()
In addition to Attempt 1, we called OSPI_phyTuneDDR() within the SBL, but there was no change in execution speed.

Attempt 3: Changing the Input Clock Divider
Divider = 8 → XIP speed was approximately 2.5 to 5.6 times slower than OCRAM
Divider = 4 → Approximately 9.0 to 18.4 times slower than OCRAM
Divider = 2 → The application failed to boot
Contrary to our expectations, reducing the divider resulted in worse performance.

Questions
1. Regarding methods to improve XIP execution speed
Is it correct to understand that the methods described in Attempts 1 through 3 above cannot be expected to improve XIP execution speed?
Additionally, if there are any additional settings required or recommended settings for improving XIP execution speed, please advise.

2. Regarding OSPI clock settings
The current SysConfig settings are as follows:
  Input Clock Frequency = 133.3 MHz
  Input Clock Divider = 8
In this case, is it correct to understand that the OSPI operating clock is 133.3 MHz ÷ 8 = approximately 16.6 MHz?

Requested response date: October 19, 2026

  • 0
    TI__Expert 3510 points

    Hi Makoto-san,

    Answer1
    Yes, you are correct about Attempt1, but in Attempt 3 if you are using PHY mode divider value doesn't matter.

    Answer 2
    Yes if you are not using PHY mode.

    I am unable to view the SysConfig Settings which you shared (unable to open the image , assuming you are using 8D8D8D protocol)

    Can you try enabling L2 Cache



    you can refer to  

    "\examples\benchmarks\optiflash_benchmark\flash_xip_l2_cache_8k"

    and below is the link to the documentation

    AM263Px MCU+ SDK: Optiflash XIP Benchmark with 8KB L2 Cache





  • 0 in reply to Lakshya Verma
    Prodigy 90 points

    Thank you for your response.

    We apologize for the inconvenience. We are resending the SysConfig screenshots.

    We would also appreciate your clarification on the following additional points.
    1. Performance with PHY Mode enabled
    In general, we understand that enabling PHY Mode allows higher-speed OSPI operation and may improve XIP performance. However, in our evaluation, we did not observe any performance difference between PHY Mode being enabled and disabled.
    Is this behavior expected under certain conditions?

    2. Performance with L2 cache enabled
    Based on the sample you provided, we enabled the L2 cache and repeated the evaluation.
    As a result, the execution performance with the L2 cache enabled was equivalent to that with the L2 cache disabled.
    In addition, we evaluated the system with L2 cache sizes of 8 KB and 256 KB. However, no change in XIP execution performance was observed in either case.
    Is this behavior also expected under certain conditions?
    The SysConfig settings under “Layer2 Cache (RL2)” are shown in the attached screenshot.

    Requested response date: October 22, 2026

  • 0 in reply to makoto yamashita
    TI__Expert 3510 points

    Hi Makoto-san,
    Generally, it works.
    May I know are you using TI's LaunchPad/ControlCard or your custom board for evaluation?
    I will replicate this on my end.

  • 0 in reply to Lakshya Verma
    Prodigy 90 points

    We are using a custom board for the evaluation.
    In addition, we are using an IS25LX128 flash device. Could this flash device be contributing to the issue?

    We would appreciate it if you could review the evaluation results for the PHY mode and L2 cache.
    Please let us know if you require any additional information.

    Requested response date: October 23, 2026.

  • 0 in reply to makoto yamashita
    TI__Expert 3510 points

    Hi Makoto-san,
    After enabling PHY, performance should be improved.
    Are you facing same issue with TI's board also if you have (LaunchPad/ControlCard)

    Can you please check the board's PHY, if it being enabled properly . 

  • 0 in reply to Lakshya Verma
    TI__Mastermind 27132 points

    Hi Makoto-san,

    1. Can you please share your bootloader logs. Do you see PHY tuning failures in Bootloader (in logs) at 133MHz?

    2. Can you please share how you are loading the application binaries to the AM263Px device?

    makoto yamashita said:
    Attempt 3: Changing the Input Clock Divider
    Divider = 8 → XIP speed was approximately 2.5 to 5.6 times slower than OCRAM
    Divider = 4 → Approximately 9.0 to 18.4 times slower than OCRAM
    Divider = 2 → The application failed to boot
    Contrary to our expectations, reducing the divider resulted in worse performance.

    if you see the internal divider changing performance, the PHY mode is not getting enabled. When PHY is enabled, this should get ignored. 

    makoto yamashita said:
    2. Performance with L2 cache enabled
    Based on the sample you provided, we enabled the L2 cache and repeated the evaluation.
    As a result, the execution performance with the L2 cache enabled was equivalent to that with the L2 cache disabled.
    In addition, we evaluated the system with L2 cache sizes of 8 KB and 256 KB. However, no change in XIP execution performance was observed in either case.
    Is this behavior also expected under certain conditions?
    The SysConfig settings under “Layer2 Cache (RL2)” are shown in the attached screenshot.

    As long as you have code placed in Flash for XIP that can be cached, RL2 should help you improve performance. Pls ensure that the MPU region is marked as cached in sysconfig. If you want to check if RL2 is working at runtime, you can check the register in the image below, which will indicate if there are any cache hits for RL2 cache, when executing from Flash:

    Regards,
    Shaunak