Hello Forum,
for a certification process according EN 501xx standards I need to know if and how the data and instruction caches are protected. A detailed description is given in Cortex R4 Technical Reference Manual in Figure 2-1 (Processor block diagram). There is mentioned the Level one memory system and the Level two interface. The R4 TRM mentions for the L1 memory System "parity or ECC supported on local memories". The TRM also mentions this is configuration dependent.
Q:
How is the Data / Instruction Path safety given from the ATCM/BxTCM -> caches -> Processing unit and the way back to BxTCM. Is Data protected when a write occurs and data is buffered in a cache Line?
regards,
Lorenz
