Part Number: AM2612
Other Parts Discussed in Thread: LP-AM261,
Hi TI Team,
We are developing an EtherNet/IP adapter using the LP-AM261 EVM and have encountered several technical questions. We would appreciate your clarification and guidance on the following items:
1. Industrial Comms SDK & Pinmux
-
SDK Version Alignment: When will the Industrial Communications SDK (Ind-Comms SDK) be released to support MCU+ SDK 26.01?
-
Pinmux Generation Bug: In version 26.01, unlock/lock sequences were added to
pinmux_config.c.xdt, butDRV_PRUICSS_init()still performs raw writes to locked registers. Has this been fixed in the corresponding release, and are there any other similar paths?
2. WWDT1 Access on Core 1
-
When Core 1 accesses WWDT1 (
0x52101000), a precise data abort occurs (even with direct JTAG loading). -
What are the prerequisites or conditions for Core 1 to access its own WWDT1? What is the default firewall configuration for it?
3. EtherNet/IP Stack Capacity
-
We found that the total CIP connections are limited to 29 (34 slots minus 5 reserved for startup), and the TCP connection limit is 9 (compile-time constants in the pre-compiled library).
-
Is this the expected design? Are there higher-capacity versions, configuration options, source code licensing options, or official guidelines to reserve Class 1 capacity?
4. tiarmclang Compiler Behavior
-
With
tiarmclang4.0.4.LTS, we suspect a code generation issue wherestrcmpis compiled into amemcmpreferencing an incorrect location. We can provide a 20-line minimal reproducible example if needed.
5. PORz RC Circuit Design
-
In both Rev A and Rev E2 schematics, R40 is $49.9\,\Omega$ and C40 is ~0.01 µF (yielding a time constant of ~0.5 µs), which differs by three orders of magnitude from the "1 ms delay" recommended in the User Guide.
-
What is the engineering design intent behind this circuit?
6. Additional Technical Clarifications
-
VIM (Vectored Interrupt Manager): If an interrupt pulse is re-triggered while it is already in the pending state, are the pulses combined/merged?
-
Memory Attributes: Do you support cross-core exclusive memory attributes?
-
Debugger/CIO Stalling: When a debugger is connected, why does CIO cause the core to stall for 100 ms to 1 s?
Thanks for your support!
Best regards,
Daniel
