Part Number: AM2732-Q1
Other Parts Discussed in Thread: AM2732, TMDS273EVM

AM2732: How to Enable and Measure the 40 MHz OSC_CLK_OUT Signal?

Hello TI Team,

I am working with the AM2732 (ZCE package) using MCUPLUS-SDK 11.02.00.25. My hardware is the TMDS273EVM evaluation board which have an external 40 MHz crystal connected to the CLKP/CLKM pins.

I would like to enable the OSC_CLK_OUT signal and measure the 40 MHz reference clock at the corresponding output pin (OSCCLKOUT, ZCE ball T4).

However, I currently measure 0 V at the output pin.

1. Configuration and software environment

• Device: TMDS273EVM

• Package: ZCE (285-pin)

• SDK: MCUPLUS-SDK 11.02.00.25

• Reference clock: External 40 MHz crystal

• Output pin: OSCCLKOUT (ZCE ball T4)

• VIN_18CLK supply: Verified at 1.8 V

• Development environment: CCS 20.4.1

• Starting project: Clock Measurement example

2. Register configuration

I am attempting to configure the following register:

ANA_REG_CLK_CTRL_REG1_XO_SLICER

Address offset: 0xC00

I unlock MSS_TOPRCM using the following sequence:

CSL_REG32_WR(CSL_MSS_TOPRCM_U_BASE +
             CSL_MSS_TOPRCM_LOCK0_KICK0, 0x01234567U);

CSL_REG32_WR(CSL_MSS_TOPRCM_U_BASE +
             CSL_MSS_TOPRCM_LOCK0_KICK1, 0x0FEDCBA8U);

The relevant register fields are:

OSC_CLKOUT_DRV       // Bits 27:24
OSC_CLKOUT_CLRZ_DIV  // Bit 28
OSC_CLKOUT_FREQ_SEL  // Bits 30:29
OSC_CLKOUT_EN        // Bit 31

The register readback currently gives:

The output remains at 0 V.

3. Questions

I would appreciate your guidance on the following:

1. What is the correct configuration of ANA_REG_CLK_CTRL_REG1_XO_SLICER to enable OSC_CLK_OUT and output the 40 MHz crystal reference clock?

2. Does the output require any additional pin configuration or initialization sequence?

3. Does MCU suppose to generate the 40 MHz frequency clock on power-up, by default?

Best regards,

T.M.