PLL Configuration in HalCoGen

Other Parts Discussed in Thread: HALCOGEN

Hello,

I'm using HalCoGen 3.0 and currently configuring the PLL1. I have to admit that the configuration is quite comfortable, but also a bit confusing. For example, I'd like to achieve reset on PLL slip. Therefore, I select the checkbox "Reset on PLL Slip". The code generator provides the following code:

    systemREG1->PLLCTL1 =  0x80000000U 
                        |  0x40000000U 
                        | ((1U - 1U)<< 24U) 
                        |  0x00000000U 
                        | ((6U - 1U)<< 16U) 
                        | ((120U - 1U)<< 8U);

which really enables "Reset on PLL slip", disables "Bypass on PLL Splip" and 

disables "Reset on Oscillator Fail". So far good, but SPNU499 on page 387 

says that BPOS must be enabled in order to use Reset on Slip (ROS) functionality. 

However, this is not the case, because 0x40000000U sets the bits 30-29 to 2h, 

which meas that Bypass on PLL slip is disabled.

Of course, one can

set the checkbox "Bypass on PLL Slip" in HalCoGen , and the issue is resolved, 

but in this case is the PLL configuration via HalCoGen rather confusing ...

Regards

 Vaclav