Hello
I am trying to use Expansion bus module in TMS470R1B1M to interface with external flash memory (64MB Spansion Paraller-NOR Flash). Configured EBM as per SPNA101 & SPNU222C application notes Attached file ebm.c is the EBM initialization file. When I write to the address in the expansion bus from my main routine in main.c, I don't see any thing on the io pins.
S29GL512P is interfaced to TMS470 using
26 pin address bus / expansion bus (EBADDR0-EBADDR18 & HET0-HET6) to A0-24 on Flash memory &
16-bit data bus(EBDATA0-EBDATA15) to DQ0-15 on Flash memory
EBCS5 to CE on Flash memory
EBOE to OE on Flash memory
EBWR0 to WE on Flash memory
I2C2SDA to ACC/WP on Flash memory
I2C2SCL to RESET on Flash memory
GIOA3 to RY/BY on Flash memory
Am I missing any thing here? Do you have any example of using Expansion bus module, for external flash memory.
Thanks
- Prasad
= ====================ebm.c============================
#include <intrinsics.h>
#include "iotms470r1b1m.h"
#include "tms470r1B1m_bit_definitions.h"
#include "basic_functions.h"
void emb_init(void)
{
// Expansion bus DMA request signals are not mapped to the i/o pins
EBDMACR = 0x00;
// 7:0 EBDMAREQ[7:0] = 0x00; none mapped to the i/o pins
// Added to the main routine to setup the EBM registers for Writing
EBMCR1=0x02; // EBM Control register
// 7:6 Reserved = 00; Reserved
// 5:3 0 = 000; 0 by default
// 2:1 DSIZE = 01; 16 bit Data bus width
// 0 LPM = 0; Low power down mode; Module is not Locally powered down
EBRWCR=0x7F; // EBM Read/Write Control Register
// 7 EBHOLD = 0; The HOLD not mapped to an external device
// 6:3 EBCS[3:0] = 1111; EB Chip Selects [3:0] mapped to the Mux Output
// 2:1 EBWR[1:0] = 11; EB Write Enable bits [1:0] mapped to the Mux Output
// 0 EBOE = 1; The Output Enable bit mapped to the Mux Output
//The next four Registers Map Addresses [29:0] to the Mux Output
EBACR1=0x3F; // EBM Address Control Register [5:0]
// 7:6 EBWR[3:2] = 00; EB Write Enables EBWR[3:2] NOT mapped to the Mux Output
// 5:0 EBADDR[5:0] = 11111; EB Address Lines EBADDR[5:0] are mapped to the Mux Output
EBADCR=0xFF; // EBM Address/Data Control Register
// 7:0 EBDATA[15:8] = 11111111; Data lines EBDATA[15:8] are mapped to the mux output. (In 16-bit Mode)
EBACR2=0xFF; // EBM Address Control Register [13:6]
// 7:0 = EBADDR[13:6] = 0xFF; EBaddress Lines EBADDR[13:6] are mapped to Mux Output. (In 16-bit Mode)
EBACR3=0x1F; // EBM Address Control Register [21:14]
// 7:0 = EBADDR[21:14] = 0x1F; EBaddress Lines EBADDR[18:14] are mapped to Mux Output. (In 16-bit Mode)
// and address lines [25:19] are mapped to GPIO / HET
//The next Register Maps the 8 bit Data to the Mux Output
EBDCR=0xFF; // EBM Data Control Register D7:D0
// 7:0 = EBDATA[7:0] = 0xFF; EBData Lines EBDATA[7:0] are mapped to Mux Output.
// Data Lines D7:D0 are Mapped to the Mux Output
// Write control register
WCR0 = 0x0001;
//15:2 = Reserved = b0000 0000 0000 00; Reserved bits
//1 = WTWSOVR = b0; Wait trailing state over ride - Atleast one traling state (not defined by TWS)
//0 = WBENABLE = b1; Write buffer enable
//Bits 7:4 control the wait states therefore only 0xF wait states are available.
//Choose only one of the following for generating internal Wait States.
// SMCR5 = 0x0004; //8-bit data width/External/Big Endian/1 wait states
// SMCR5 = 0x0014; //8-bit data width/External/Big Endian/1 wait states
// SMCR5 = 0x0024; //8-bit data width/External/Big Endian/2 wait states
// SMCR5 = 0x0034; //8-bit data width/External/Big Endian/3 wait states
// SMCR5 = 0x0044; //8-bit data width/External/Big Endian/4 wait states
SMCR5 = 0x0035; //16-bit data width/External/Big Endian/3 wait states
// 15:14 = Reserved = b00; Reserved bits.
// 13:12 = ASC = b00; Address Setup time Cycles - ASC. Setup time = 0.
// 11:9 = TWS = b000; Trailing Wait States - TWS. = 0.
// 8 = Reserved = b0; Reserved bits
// 7:4 = WaitStates = b0011; Wait States = 3 wait states.
// 3 = END = b0; CPU is in big endian mode (in read mode)|
// 2 = MLOC = b1; Memory location - is on the Expansion bus
// 1:0 = DW = b01; Data width is 16-bit data
// Memory Map setup
// added to the low level init file with the memory mapping code
// activate Expansion bus at 0x00500000 set size to 512KB
MCBAHR2 = 0x0050; //EBM RAM base addr at 0x00500000
// 31:16 = Reserved = x0000; Reserved bits
// 15:0 = Address[31:16] = x0050; Base Address bits 31-16
MCBALR2 = 0x0050; // Size of 512KB
// 31:16 = Reserved = x0000; Reserved bits
// 15 = Address[15] = b0; Base Address bits 15
// 14:10 = Reserved = b00000; Reserved bits
// 9 = AW = b0; Auto wait on write, disabled - write operation is completed in one cycle
// 8 = Reserved = b0; Reserved bits
// 7:4 = Blocksize = b0101; Block size is 512KBytes with CPU address bus lines compared Address[32:19]
// 3 = Reserved 0 = b0; Reserved bits - Must be set to 0
// 2 = Reserved = b0; Reserved bits
// 1 = RONLY = b0; Read Only Protection
// 0 = PRIV = b0; Privilege protection
}
