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Strange PWM behavior during ramping of duty cycle

I am experiencing a strange behavior of the PWM signal during ramping of the duty cycle value on my LM4F232H5QD board. My PWM generators are running at 20 kHz in synchronized mode, and I am updating their duty cycles every 250 us (4 kHz), the PWM period is 4000. When I do a ramp of the duty cycle from MIN (0) to MAX (3999), the output signal looks very strange towards the end. In the attached image the purple signal is the duty cycle, the green signal indicates that my duty cycle counter wraps around to zero again, and the turquoise signal is the PWM output lowpass filtered. 

I would expect the PWM output to go from completely off (0) to 100% (at 3999) when I ramp the duty cycle. What I do not really understand is 

1) Why is the PWM signal still 100% after my counter wraps around and starts counting from zero?
2) Why is there one PWM period of 0% duty cycle? The duty cycle is updated just before it dips, and then the PWM signal goes 100%-0%-100% before the next update.

  • SWAG here - may stimulate further thought...  ARM MCUs have experienced some anomalies @ both (high-low) PWM extremes.  Perhaps of value to limit your PWM range to 3-5 counts offset from min and max.  (lowest PWM = 3, highest PWM = 3997) and see if/how this effects your observation.

    Concerned that "wrap around" (green) is SO wide!  (300uS - if I read your trace correctly) 

    May assist diagnosis if we can see a "good" trace (mid-range) which displays duplicative settings/waveforms.  Also helpful to review your code for over-flow/other illegals @ critical "hi/lo" PWM generator settings...

  • It's not really an issue of there being an ARM core in the MCU, but rather the design of the PWM generators.

    Complex PWM generators often have trouble hitting 0% and/or 100% output.  Simple PWM generators can usually hit both extremes.  It has to do with the fact that the complex PWM generators implement a state machine that changes states when the counter matches a compare value, as opposed to a simple PWM generator where the output can be the direct result of a magnitude comparison between the counter and compare value.

      At one of the extremes, the compare value will never match the counter.  For a PWM with a period of 10, for instance, the counter can have 10 possible values, but there are 11 possible output percentages that you could want: 0%, 10%, 20%, 30%, 40%, 50%, 60%, 70%, 80%, 90%, 100%.

  • slandrum said:
    not really an issue of there being an ARM core

    Disagree!  1) Firm/I have noted very similar behavior in 3 "non-LMI/TI" ARM MCUs and 2) Client can't really move now towards a non-ARM, complex PWM, capable MCU can he?

    Believe that my "work-around" of bounding both lower/upper PWM extremes has a very good chance of success.  Can't really understand what you are otherwise proposing...

  • I'm not proposing anything, just noting that the issues with the PWM peripheral design are independent of the CPU core.  I've run into similar issues with PWM generators on non-ARM MCUs.

    I don't want the PWM peripheral design to be thought of as tied to the ARM core in any way.  It may be that all ARM based MCUs with PWM modules have this issue, but it's not because they have ARM cores.  It's likely to be an issue with any of the more recent MCUs as motor control and other applications often want a complex PWM peripheral.  I just wish these PWM peripherals also supported a "simple comparator" mode, so that applications where all you are really controlling is the duty cycle could hit the 0% and 100% outputs without having to do a lot of contortions in the software to prevent glitches on the transition to/from the extremes.

    And come to think of it, there is one ARM based MCU, the PSoC5 family from Cypress, where you can have simple PWM generators.

  • slandrum said:
    more recent MCUs as motor control and other applications often want a complex PWM peripheral.

    Complete agreement here.  My group migrated to ARM 2005 (pre LMI) - have used 4 different ARM vendors - encountered this PWM "unwanted sensitivity" every time!  While anecdotal - guys like you/I make our livings by detecting such linkages - profiting from such experience.  Maddening when 1st encountered - thus my advice to original poster.  (Slay the dragon while having already slayed similar dragon...)

    Should state that the "bounding" method I previously described has worked well in multiple motor control/power-type applications.  I can accept the need for 0° duty cycle (which we achieve by gating our MCU's PWM output) but we've yet to encounter a situation where 99+% PWM was not, "good for gov't work!"  (as opposed to full-on - 100° duty)

  • Very interesting information from both of you. I have done some experimenting with limiting the bounds of the PWM signal, and indeed when I run up to 3997 instead of 3999 it works perfectly. I will use this as a workaround for now and hopefully it won't affect the operation of the device too much. About the long wrap around time; I set a pin high when my counter value % PWM_MAX is equal to zero, hence it will stay high until the next duty cycle update.

  • cb1_mobile said:
    limit your PWM range to 3-5 counts offset from min and max.

    Perhaps such instant diagnosis warrants the, "Verified Answer" tick?

  • I was hoping to get an "official" reply from TI on how this really works, before marking it as verified (I'm guessing they don't really look at the threads which have been marked as answered already).

  • Pelle Windestam said:
    official" reply

    But of course - mon ami.  Bit pressured as inventory of low-thread-count T Shirts & leaky mugs plunging - but will try - soldier on...  (fast, accurate, detailed fix (again) - I'd seek to encourage...)