Audio Playout on LM4F232

Akshaya Mukund said:

Does the board support a DAC in any way?

You may employ serial (I2C, SPI) based external DACs or parallel DAC (for faster data rates).  Devil in the details of your spec (which somehow - escaped your post)

Suggest that you attach headphone jack to the small, "out-board" DAC board you build & add - maintaining the integrity of your fine 4F Eval board...

Akshaya Mukund said:

I am new to development on Stellaris and have just obtained an LM4F232 Evaluation board. It does not come with a DAC so I was wondering if there is some sort of work-around to this. Does the board support a DAC in any way. My aim is to try an achieve audio playout, with what I have and some add-ons would it be possible (could a headphone jack be attached to the board in some way)?

Thanks and Regards

I haven't used this microcontroller before, but if it has I2S then connecting it to a serial audio DAC is easy.  The CS4335, for example, is a simple 8 pin audio DAC you could use.

jrmymllr said:

if it has I2S

No I2S this M4 MCU (why I suggested I2C, SPI).  Is CS4335 confined to I2S?  If not - as resident forum audio guru would you be good enough to suggest better fit DAC?

cb1_mobile said:

if it has I2S

No I2S this M4 MCU (why I suggested I2C, SPI).  Is CS4335 confined to I2S?  If not - as resident forum audio guru would you be good enough to suggest better fit DAC?

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Technically the CS4335, or any I2S DAC, can be used with SPI, as I proved when using with a LM3S6965 (before the LM3S9B9x came along).  I2C is too slow and not really meant for this type of thing.  Since the OP might want to output decent quality audio, they will likely want a hardware-buffered output like SPI or I2S otherwise the CPU will be practically I/O bound.  Also, all audio DACs I've seen are I2S or some other serial link.  They should check for other types available.  But anyway, so how to use SPI in place of I2S?

I2S is essentially SPI, with the addition of another clock signal, MCLK, and and a "word select", WS or LRCK.  MCLK is a multiple of the serial clock, usually 128X or 192X, or even higher.  It's used for the DAC's linear interpolation.  WS or LRCK is a signal that flips back and forth to indicate if the left or right channel is being transmitted. 

The trick to this is to use two PWM channels to generate MCLK and LRCK.  That's easy, actually the trick is in synchronizing the PWM with SPI.  That can be done with delays and trial and error. 

Wow - great I2S detail - much appreciated - thank you...  (have successfully avoided I2S thus far)

New M4 has some 50 additional PWM config registers (compared to M-3) - hope this can greatly reduce/eliminate dreaded, "trial & error," you note.  Again - merci, mon ami...

Very detailed. I am guessing you implemented something similar for LM3S6965 (DAC with SPI). If you have this would give me a great deal of confidence going ahead.

Also just to better understand what you mentioned above. So the SPI is the serial port interface containing audio data (say 16-bit PCM data). This would be transmitted to the DAC and the MCLK handles this transmission with the WS (LRCK) being an indication to the DAC to differentiate between left and right.

Further to generate MCLK and the WS, 2 PWM channels will need to be used (which are derived from the system clk ?) that would have to be compatible with the DAC's specifications (for serial data input).

Also would it be possible for anyone to share some resources on SPI learning that you found helpful. I am looking for a way to speed up my implementation.

Akshaya Mukund said:

Very detailed. I am guessing you implemented something similar for LM3S6965 (DAC with SPI). If you have this would give me a great deal of confidence going ahead.

Also just to better understand what you mentioned above. So the SPI is the serial port interface containing audio data (say 16-bit PCM data). This would be transmitted to the DAC and the MCLK handles this transmission with the WS (LRCK) being an indication to the DAC to differentiate between left and right.

Further to generate MCLK and the WS, 2 PWM channels will need to be used (which are derived from the system clk ?) that would have to be compatible with the DAC's specifications (for serial data input).

Also would it be possible for anyone to share some resources on SPI learning that you found helpful. I am looking for a way to speed up my implementation.

Yes you're correct.  If we're talking about generating audio only (no audio input), and if I use the CS4335 pinout for example, LRCK, SDATA, SCLK, MCLK:  SDATA and SCLK connects right up to SPI data out and clock out, respectively.  LRCK and MCLK would have to be generated with PWM. 

For 16 bit stereo PCM, LRCK would change states every 16 bits.  MCLK could be 128*44100 if it's 44.1KHz audio, or 5.6448MHz.  This could all come from the system clock as everything is a nice multiple of each other. 

So for 44.1KHz stereo, SCLK ends up being 44100 * 2 channels * 16 bits = 1.4112 Mbits/s.  I have my old code for the 6965, but I don't know if it'll help you.  In brief what I did was create a 2-dim array.  It had columns for the PWM divisor for MCLK, LR, and a column for the bitrate and synchronization delay, which I'm sure if very processor dependent.  Each row was a different bitrate setting.  Then a function was passed the required bitrate (or sample rate) and it set up parameters based on this.