How to generate interrupt(with peripheral)

Hi Zhaohong Zhang

Thank you very much for your quick reply !!

Ok the points 1,2 and 3 are good for me.

For the point 4 are you sure that it is R4 ? Can you give me more detail on this point 4 please ?

Thank you very much,

Kind Regards, 

Florian,

R4 hardware vector mode can be enabled by the following assembly code.

HW_Vec_Init
    stmfd sp!,{r1,LR}
    MRC p15 ,#0 ,R1 ,c1 ,c0 ,#0
    ORR R1 ,R1 ,#0x01000000     ;mask 0-31 bits except bit 24 in Sys Ctrl Reg of CORTEX-R4
    MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0   ;enable bit 24
    ldmfd sp!,{r1,PC}

Thanks and regards,

Zhaohong

Thank you very much Zhaohong Zhang for your help

I will try to enable these interruptions!

Florian 

Thank you very much, it works perfectly!!

I know this is an old thread, but I have a question about this.

I'm writing C-code for the RM4. And I need interrupts.

Do I really have to enable interrupts this way? Using assembly???

Isn't there a C-code function for that?

If not, how do I use those assembly lines?

Cor,

R4 system control registers can only be accessed in in assembly code. You can put the following code in a .asm file

 .global HW_Vec_Init

HW_Vec_Init
    stmfd sp!,{r1,LR}
    MRC p15 ,#0 ,R1 ,c1 ,c0 ,#0
    ORR R1 ,R1 ,#0x01000000     ;mask 0-31 bits except bit 24 in Sys Ctrl Reg of CORTEX-R4
    MCR p15 ,#0 ,R1 ,c1 ,c0 ,#0   ;enable bit 24
    ldmfd sp!,{r1,PC}

Add the following in your c-code,

extern void HW_Vec_Init();

Then, you can call this function in the c-code.

Thanks and regards,

Zhaohong

Zhaohong,

I traced this old thread for using interruption for TMS570.  

I have made the GIOA interruption as IRQ running very well.

Now, I want to try setting the same GIOA interruption to be FIQ to see if any benifits to reduce delay.

To set GIO interrupt A to be FIQ.  I changed FIRQPR0 bit-9 from "0" to "1" and remained all the rest unchanged.

The MCU did not ran into ISR.

Could you tell me what else I should do to implement the change from IRQ to FIQ?

Thanks,

Yanzhong

Yanzhong,

(1) You need to clear the F bit in CPSR to enable FIQ.

(2) FIQ does not support hardware vector mode.

Thanks and regards,

Zhaohong

Zhaohong,

(1) You need to clear the F bit in CPSR to enable FIQ.

Do I have to use Assembly language instructions to clear F bit in CPSR?

(2) FIQ does not support hardware vector mode.

Please confirm if my understanding below is correct.

The FIQ's ISR entry point is 0x0000001C.  When multiple FIQs are set, inside the FIQ ISR, the CPU branches to the interruptions based on the vector offset in FIQINDEX

Thanks,

Yanzhong

Yanzhong,

(1) You have to use assembly code to clear this bit in the same way as you enable IRQ.

(2) There are two ways to handle FIQ the first one is S/W vector mode. You need to have this code at address 0x1C. "ldr pc,[pc,#-0x1b0]". CPU will jump to the address defined in the VIM RAM. In order to make it work correctly, you cannot put a breakpoint at 0x1C. The second way is legacy mode. You put "B _FIQ_ISR" at 0x1c and do all processing in FIQ_ISR.

Please do not continue on a closed thread next time. You can open a new thread and refer to the closed thread in your question.

Thanks and regards,

Zhaohong

Zhaohong,

Sorry, I did not find the way how to start a new thread. (I remebered there was a "new post" button somewhere before. But now I cannot find it)

Or, please split my question to start a new thread. - "TMS570LS3137  FIQ for GIOA interruption"

Now, (1) I defined my GIOA interruption ISR entry point as FIQ_ISR entry point at 0x1CH. (2) I enabled the FIQ by clearing 'F' of CPSR.

I can get the CPU enter into the FIQ_ISR.

My problem is that once the 1st signal rising edge at GIOA pin triggered the interruption (after the IAR IDE programmed the flash), the FIQ ISR was repeated by itself without the trigger signal (input at GIOA remains HIGH), and not be affected by the GIOA trigger signal any more. It repeats at a fixed frequency (about 510KHz, my system clock is 180MHz).

I do not think there are any problems about my GIOA pin settings because the GIOA interrupt worked very well as ISR interrupt.

What I can see in REQEANSET0 was the interrupt channel 0 and 1 were set automatically. So I guess it's the Phantom interruption channel caused this.

Then I tried to add a "if" condition instruction in the FIQ ISR to check if the FIQINDEX =0x0000000A. - Yes, it is it every time.

Hope to get your analysis or comments on this.

By the way, we bought the TMS570LS31x Hercules Development Kits. The user guide lists its schematic, but not actually has it attached.

Could you please provide me the schematic? We need it to discuss with IAR about their probe connector.

Thank you,

Yanzhong

Yanzhong,

Did you clear GIO interrupt flag from the GIO module in GIO ISR?

Thanks and regards,

Zhaohong

Thanks! Zhaohong,

Just FYI. Clear GIO interrupt flag is one of the two related factor. (I commented it out during different try)

At same time, I have to use a "if statement" to check FIQINDEX and branch it in FIQ ISR. Otherwise, the repeating interrupt still occurs.

With this extra "if statement" delay, the overall perfermance using FIQ method is similar to that using IRQ method.

Regards,

Yanzhong