Hi,
I'm using CCS v5.1 with LM4F232H5QD with sysclk set to 1Mhz.
I'm compiling the same code with CCS and IAR and I see different SPI behavior with the CCS compiled version.
The issue arises during the first SPI transfer between the host and a specific module. The SPI transfer is with the help of DMA.
I notice two strange behaviors:
1. My first SPI write is 4 bytes, 50 ms pause and then write 6 byte. I can see on the scope the first 4 byes correctly, but then I can see only 4 bytes out of the 6. (clock was 1khz confirmed to the scope).
2. I divided the 6 bytes to 4 and then 2 bytes (meaning 4 bytes, then another 4 bytes and the 2 bytes left) and then the written was successful (?). The next action is SPI read from the module. Suddenly I see that the clock dropped to 8KHz.. When I reviewed the registers I say that SSI_CPSR (the divider) was change from 0x2 to 0xFE. It was change exactly during activating MAP_SSIDMAEnable().
Is there any reason why I can’t transfer more than 4 bytes on the SPI?
Is there any reason why the divided is overwritten?
I just want to mention that the same code exactly works perfectly when compiling with IAR - none of these phenomenons happens.
Thanks for your help!
Yael