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MibSPI

ajay reddy1
Prodigy 200 points

Hi,

On my board for SPI1 two slaves are connected (HI3593 and HI6121). Here my slaves support 8-bit data format.  From my master (TMS570) if am sending 5 bytes (1 opcode + 4 bytes) to the slave, will the CS of the controller holds LOW till the transmission (for all 5 bytes) complete? Here "CSHOLD" bit  (28th bit) of Multi-buffer RAM transmit data register says "CSHOLD bit is supported in compatibility mode of MibSPI".

And I configured "CHARLEN[4:0]" as 8-bits in SPIFMT register. I want to know does CSHOLD bit usefull in MibSPI or not? And If TG0 (transfer group0) is having 32 bytes of data can I transmit all 32 bytes of data in oneshot without CS going high between byte to byte (when CHARLEN[4:0] is configured for 8 bit data length).

 

Thanks & Regards.

  • 0
    TI__Guru 59540 points

    Hello Ajay,

    For the MibSPI in master mode, the CS will remain asserted when the CSHOLD bit is set in the first transmission and subsequent transmitted words indicate the same CS regardless of the state of the CSHOLD bit in the subsequent messages. When this is done, any T2CDELAY or C2TDELAY settings will be ignored but WDELAY will still be honored. CSHOLD works as described in both compatibility and buffered modes.

    Note:

    T2CDELAY = chip select hold after a transaction

    C2TDELAY = chip select setup time delay prior to a transaction

    WDELAY = delay between transactions

    If this answers your question, please indicate so by validating the answer.

    Thanks and Regards,

    Chuck Davenport

  • 0 in reply to Chuck Davenport
    TI__Mastermind 22375 points

    Ajay,

    I will try to reply to the second part of your question.

    The buffer in MIBSPI mode are 32bits. That does not mean that the transmission will always be 32bits.
    It depends on the way the format for a given transfer group is programmed.

    In your case, if the format is 8 bits, that the transmission will be 8 bits.
    The data you have to write in the MIBSPI transmit buffers will have to be right aligned. (bit 0 to bit 7)
    If you have defined n buffers for a transfer group, and are using CS, the CS will stay asserted low for the transmission of the n buffer as explained by Chuck.

    Best Regards,

    Jean-Marc

  • 0 in reply to Chuck Davenport
    Prodigy 200 points

    Hi Chuck,

    If my understanding is right, In Multi-Buffer mode CS will stay LOW till complete Transfer Group is transferred, if CSHOL bit is SET. But as per TRM CSHOLD description says, CSHOLD bit is supproted in master mode only in compatibility-mode of MibSPI.

    Thanks & Regards,

    Ajay.

  • 0 in reply to ajay reddy1
    TI__Guru 59540 points

    Hello Ajay,

    Can you provide the part number of the specific TMS570 device you are using and also the TI literature number (SPNUxxx)  you are referencing?

     

    Thanks,

    Chuck D.

  • 0 in reply to Chuck Davenport
    TI__Mastermind 22375 points

    Ajay,

    Can you provide the requested information?
    This thread is open for more than 2 weeks and we need to close it if your question has been answered.

    Thanks and Regards,

    Jean-Marc