CPU Compare Module mismatch error on Hercules TMS570LS31x HDK

Zeeshan Aslam

Other Parts Discussed in Thread: HALCOGEN

Sometimes when I connect to board via XDS100v2, set status bit shows CPU mismatch condition. It disappears after a number of target resets. As far as I know it is recommended to Initialize Cortex-R4 core registers to same initial values to avoid this but why CCM reports such error even after resetting the target, right after the debugger is connected to target core. How can I prevent this to happen?

over 14 years ago

0 Zeeshan Aslam over 14 years ago

Prodigy 150 points

Result of this compare mismatch condition is continuous assertion of core FIQ interrupt line.

0 Jean-Marc Mifsud over 13 years ago in reply to Zeeshan Aslam

TI__Mastermind 22375 points

Zeeshan,

Because of the lockstep implementation, it is necessary to initialize all the CPU registers.
If you are using HalCoGen, this initialization is done in the startup code.

On Cortex R4F only the CPSR_SVC and PC registers have a defined state after reset.
All others registers (Including the VFP) are untouch by reset.

Please can you confirm that you are doing this initialization using Halcogen generated code?
If not, please provide your initialization code and also explain when this code is executed.

Thanks and Regards,

Jean-Marc

0 Jean-Marc Mifsud over 13 years ago in reply to Jean-Marc Mifsud

TI__Mastermind 22375 points

Zeeshan,

What is the status on this thread?

Please mark it as Verified Answer if we answered your question.

Regards,

Jean-Marc

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CPU Compare Module mismatch error on Hercules TMS570LS31x HDK