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RM48 ISR Structure

HanSeoung Lyoo
Intellectual 320 points

Hi, TI.

 

I used to RM48HDK, CCS4.1 and Halcogen 3.00.10.

 

My plan will make two of the ISR by RTI module.

The interrupt 1 is 1ms ISR by RTI module(:RTI Compare0),

the other interrupt 2 is 5ms ISR by RTI module(:RTI Compare1).

The priority of interrupt 1(1ms) is the 1’st, the priority of interrupt 2(5ms) is the 2’nd.

 

I want to do ISR structure, as shown in Fig.1 do want to be executing code.

 

                                                         Fig. 1

 

However, interrupt settings are shown in Fig.2~3 and ISR structure is shown in Fig.4.

                                                         Fig. 2

                                                         Fig. 3

                                                         Fig. 4

 

 

How are performed as shown in Fig.1 ISR let me know.

 

Thank you, TI.

 

  • 0
    TI__Mastermind 22375 points

    Lyoo,

    Thanks for posting on our forum.

    If I understand your problem, the execution time of your 5ms ISR lasts longer than 1ms.

    By looking to the figure 4, I assume the 5ms task is running in IRQ mode.
    In other words, it is part of your ISR handler.

    This is not really the best way to do it.
    The problem you are facing is, once the CPU is servicing your 5ms ISR, because the CPU is in IRQ mode, IRQ areautomatically disabled at CPU level.
    That means that until your are done with your 5ms task, no other request (1ms ISR) can interrupt the CPU.
    Once the 5ms task is finish, the CPU switches back from IRQ to what ever mode it was and then IRQ are enable again. If a pending 1ms is present, it will switch back in the ISR handler to service the 1ms task.

    One option could be to use only the 1ms interrupt and have a counter to flag every 5 interrupts to execute the 5ms task.

    Another option is to use an OS to perform all this for you. FreeRTOS or Micrium are 2 options that have been ported on the HERCULES family.

    The last option is to make the ISR re-entrant. This is something that can be done, but we don't have out of the box solution.

    There is some thread on this forum talking about re-entrant ISR.
    Basically, you will have to write from scratch the IRQ_ISR, and re-enable IRQ will in IRQ mode.

    Please let me know if I've clarified your problem.


    Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 320 points

    Hi, jean-Marc.

    First of all, thank you for the quick response.

     

    Interrupt configuration as shown in Figure 1(:the above my post) was well by your one option.

     

    There is one more question.


    I would try. Interrupt option was changed as follows.

    Interrupt 1 option changes IRQ -> FIQ.

    Interrupt 2 option not changes IRQ.

    So, Interrupt configuration as shown in Figure 1 was well.


    One project consists of IRQ interrupt and FIQ interrupt is not a problem?

     

    I want your response.


    Thank you.

     

  • 0 in reply to HanSeoung Lyoo
    TI__Mastermind 22375 points

    Lyoo,

    Using FIQ for your 1ms task will also fix your problem.

    Even if the CPU is servicing an IRQ ISR (in your case the 5ms task) an FIQ interrupt will be able to interrupt the CPU and jump in the FIQ handler.

    Anyway, you have to remember that on HERCULES micro controller, FIQ are in fact NMI. Once the FIQ are enabled at CPU level, it can't be disable anymore.
    So in your case, the 1ms task will always be serviced, unless you disable it from the RTI source. Trying to disable at CPU level will not work.
    IRQ can be enable/disable at anytime by accessing the CPSR register. (In privilege mode).

    Please let me know if I've answered your question.

    Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 320 points

    Hi, jean-Marc.

     

    Thank you for your help.