Hi, TI.
I used to RM48HDK, CCS4.2.4 and Halcogen03.00.01
I want that between RM48 and NVRAM are accessed by EMIF(16bits data bus).
So, EMIF module is setting by Halcogen03.00.01.
- EMIF module enable(Fig.1).
- Pin Mux Set(Fig.2).
- Only used to EMIF ASYNC1(I used to EMIF_CS[2]).(Fig.3)
- EMIF ASYNC1 setting(just check the pin of CS[2], nWE, nOE).(Fig.4)
- MPU default(Fig.5)
Fig. 1
Fig.2
Fig.3
Fig.4
Fig.5
The function of emif_ASYNC1Init() is inserted the main function(in the sys_main.c).
1) The test of EMIF reading.
To check EMIF reading, the coding(as follows) was executed by using a constant cycle interrupt(by RTI module).
Unt16Temp = *((uint16_t *) 0x60800000);
As shown below, I think correcting work.
2) The test of EMIF writing.
To check EMIF writing, the coding(as follows) was executed by using a constant cycle interrupt(by RTI Module).
*((uint16_t *) 0x60800000) = 0xFFFF;
As shown below, EMIF_nWE is generated 3 times.
What’s the problem? Answer please.
Thank you for my post reading.
