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Help:TMS570LS3137 No Divide zero abort

Supcon-Jason
Prodigy 140 points

I read the DDI0363G_cortex_r4_r1p4_trm4.pdf ,have some question about DZ bit(Divide of Zero) of System Control Register .If i set 1 to DZ bit.Then do:

U8 DIVIDE_ZeroTest(void)
{
U8 byRet = FALSE;    // U8 -->unsigned char
U32 dwTemp = 0;    
U32 dwTestVal = 0;
U32 dwBaseVal = 5;

while(1)
{
dwBaseVal = 5;
dwTestVal = dwBaseVal / dwTemp;
dwBaseVal = dwTestVal;
dwBaseVal++;
}

return (byRet);
}
it do not generate any Undefined Instruction exception??Have anyone can answer this question？Are there any En-bit should enable？Point it？thank you！！

  • 0
    TI__Mastermind 22375 points

    Mao,

    Thanks for using our forum.

    The problem you are facing is certainly because the code you are using, when compiled will use the Real Time Library to execute the divide operation.

    Ultimately, the code will execute a udiv or sdiv, but the divide function in the library checks for the divider to be different than 0.
    So whatever you set the DZ bit in the System Control Register or not, the exception does not happen.

    Here is a test code that will use the udiv directly in an assembly file. 5277.UDIV.zip
    The DZ bit is set in System Control Register and you will see that when the variable b=0 and the udiv function is called, the CPU will jump in undefine entry as expected.

    Please have a try and let me know if I've answered your question.

    Thanks and Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Prodigy 140 points

    I try your demo.The result just like you say.Then,can you tell me something about UDIV and SDIV instruction??Their Function?How to use them?The difference bewteen UDIV and SDIV??or just give me datasheet about them!

     

    thank you!!

  • 0 in reply to Supcon-Jason
    TI__Mastermind 22375 points

    Mao,

    Unless you are writing your code in assembly language (like i did in my example), you don't really care about the UDIV and SDIV.

    Our code generator will invoke these instructions when it is necessary.
    As I said in my previous post, the code generator tests the argument, and in case of a divide by 0 the instruction UDIV or SDIV is not executed.

    The UDIV and SDIV are part of the THUMB2 instruction set and are not available in ARM mode or THUMB mode.
    SDIV is a signed Divide and UDIV is Unsigned Divide.
    The syntax is:

    SDIV {cond} {rd}, Rn, Rm
    UDIV {cond} {rd}, Rn, Rm

    With:
    cond is an optional condition code.
    Rd is the destination register. If Rd is not specified, Rn will be the destination register.
    Rn is the register holding the value to be divided.
    Rm is the register holding the divisor.

    When you compile your C code, you have to select the target processor as 7R4 (this is mandatory for Cortex R4) and Designate Code State to 16 (for thumb2, the default is 32 for ARM mode)
    It is also necessary in the linker option to specify a RTS library compiled in Thumb mode. (rtsv7R4_T_be_v3D16_eabi.lib for example)

    Regards,

    Jean-Marc