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Open Drain pin influenced by Pull-Down configuration

Hello,

on our TMX570LS3137AUPGEQQ1 we use some NHET Pins as testing output for an voltage comparator.

The configuration of those are:
*) GIO
*) Open Drain
*) Direction = Output
*) GIOPSL= 0 for pull-down

By measuring on these Pins, we see that the setting of the PULDIS register does influence the voltage.

Behaviour PULL Disabled: Measured voltage as expected
Behaviour PULL Enabled: Measured voltage decreases slightly (about 0,07 V)
This minimal voltage drop leads in our case to unwanted behaviour on the voltage comparators. 
In the TRM SPNU499 is stated, that the PULL control is disabled if the pin is set to the configuration above. 
But it seems that this is not the case and we have to do it explicitly by setting the PULDIS to 1.

Is this behaviour wanted or only visible in this development chips?


BG,
Erich Ebenhoch