How to perform READ WRITE Access using 64-Bit to ECC RAM area?

Hi Pashan

Thanks for using the forum.

You can use STRD or LDRD to perform the 64b transaction. On an LDRD, you will receive the single byte of ECC replicated on all the byte lanes. Obviously, you should LDRd to 0x0840_0000 for the 1st ECC byte, then to 0x0840_0008 for the next ECC byte and so on.

For writes, make sure the bit 8 of RAMCTRL is set meaning ECC write is enabled (on both TCRAM even and odd). Then you load up 2 registers like r3:r2 with a single byte in r2. The r3 content is ignored. Then perform STRD using r3:r2 into the desired ECC byte.

Hello Abhishek,

1> So, LDMIA and STMIA with 2 Registers will not perform 64-Bit write to TCRAM Port for ECC RAM.

Is the above statement correct?

LDRD and STRD are the only solution even though Cortex-R4 TRM says something about "WRITE MERGING" to make 64-Bit access over TCRAM port when succeessive locations are accessed using any width access. Is the statement correct?

2> In your last mail following statement "Then you load up 2 registers like r3:r2 with a single byte in r2."  means which byte of 32-Bit Register? MSB or LSB or Middle bytes.

Please let me know.

Thank you.

Regards

Pashan

Pashan

I ram some sims to figure out the answer.

LDMIA and STMIA will also work. Something else to be cautious about is to disable ECC in the CPU for the time you are reading the ECC from TCRAMW. The TCRAMW does not deliver the correct ECC when you are reading ECC.

The lowest 8b of the r2 are only relevant.

Hello Abhishek,

Can you please help me understand how LDMIA/STMIA will use 64-Bit Read/WRITE Cycle?

Does that mean, LDRD and STRD need never to be used for TMS570 under any circumstance?

Or, at least under which circumstance LDRD/STRD is the only solution.

Any better explanation will help me a lot.

Eagerly waitiing to hear from you regarding the difference between LDMIA/STMIA and LDRD/STRD w.r.t. 64-Bit Access Cycle.

Thank you.

Regards

Pashan

Pashan,

My understanding from the documentation...

First of all we have to confine the discussion to TCM interface. These discussion points on L2 interface will differ.

As per the CPU doc, all TCM accesses are treated like accesses to "Normal" memory. So as such there will never be a reason the CPU will split an LDM/STM to TCM into smaller 4byte sized transfers. Hence we could claim, LDRD/STRD on a TCM interface appears to perform the same function as an LDM2/STM2. To be sure I am checking with ARM in parallel.

On L2 the MPU defined memory type will control the type of access generated and would differ between LDRD/STRD and LDM/STM.

Hello Abhishek,

Can you please tell me which one is L2 Interface Port within the TMS570LS3137 Datasheet Functional Block Diagram?

Also, CRC Registers are on which Port from CPU Perspective for TMS570LS3137 Datasheet?

When MPU is disabled, then does L2 Interface Port matter?

I don't see anything called L2 Interface Port within TMS570LS3137 Datasheet.

Please help.

Thank you.

Regards

Pashan

Hello Abhishek,

I found in r1p3 Cortex TRM following section :

Pashan

You are absolutely right. The L2 interface is the way we are getting to peripherals and SYSTEM module. THe TCM or the L1 interface is how you get to RAM and Flash.

No, MPU not being enabled doesn't make all transfers 64b width.

If the MPU is disabled, the transfer width is controlled by a combination of the instruction access size for eg. LDRB, LDRH, STRB etc and the space you are accessing. This is defined as the "Default Memory Map" in the CPU documentation. The higher address accesses i.e. beyond 0x8000_0000 are device or strongly ordered. Here the instruction access size matches the transfer size. In the lower address accesses the accesses are normal and here the width is chosen by the CPU automatically independent of the access size of the instruction.

If the MPU is enabled you can configure the region to be the way you want - strongly ordered, device, normal etc. All these are MPU settings. The definition of the region type is still obeyed w.r.t. access size.

Hello Abhishek,

1> "The higher address accesses i.e. beyond 0x8000_0000 are device or strongly ordered. Here the instruction access size matches the transfer size."

So, if I use LDRD for writing to following CRC Registers of TMS570LS3137 device [base address 0xFE00_0000]  -- TRM spnu499.pdf

60h                PSA_SIGREGL1                                 Channel 1 PSA Signature Low Register                        Section 14.4.14

64h                PSA_SIGREGH1                                 Channel 1 PSA Signature High Register                      Section 14.4.15

then it will be pure 64-Bit write to CRC and hence CRC will calculate new PSA for 64-Bit of DATA.

But if I use LDMIA for the above two registers, then I will get 32-Bit write and hence CRC will calculate 2 cycles of new CRC with 128-Bit of DATA along with padding as ZERO for 32-bits.
Are the above statements correct?
That is what I am understanding from your reply.

Please confirm.

Thank you.

Regards

Pashan

Pashan, Yeah if the CRC is configured as strongly ordered or device type (which is true if MPU is disabled because of CRC module's address) then what you are saying is true.

Hello Abhishek,

But in the code I am seeing STRD as well as STMIA to those 2 Registers is always effectively performing 64-Bit WRITE instead of 128-Bit CRC for STMIA.

Can you please simulate for TMS570LS3137 device with no MPU and let me know?

This is the mystery I am trying to solve.

One of big reason is that if STRD instruction must be used in order to have effective 64-Bit WRITE cycle to CRC Registers [2x32-Bit Registers in order], then I will have to create ASSEMBLY program as C compiler only generates STMIA instruction.

Please help me with the correct information.

According to your analysis, one is pure 64-Bit write and the other is 128-Bit write with appropriate padding.

I am seeing both having 64-Bit WRITE with no apparent difference.

Thank you.

Regards

Pashan

Pashan

On reading the CPU docs further, I read the note regarding STRD to strongly ordered and device memories. It has been clearly stated that STRD always generates 32bit transfers for strongly ordered and device memories. Of course this applies to LDRD as well. I have confirmed this behavior as well.

For normal memories, of course STRD/LDRD will truly generate 64b transfers. But in this case even the STMIA/LDMIA may get merged to generate 64b transfers.

Hello Abhishek,

That means there is no way to perform pure 64-Bit CRC Calculation on DATA STREAM without Padding with ZEROS.

Is the above statement correct?

Thank you.

Regards

Pashan

Pashan, you could of course use the DMA in Auto or Semi-Auto modes of the CRC to get 64b calculation and then no need to pad with zeroes. This is documented in the device TRM in CRC chapter "CRC modes of operation".

Hello Abhishek,

There is no DMA in the newer device XXXXXX.

That is why I am asking this question.

So, for a Device without DMA or for TMS570LS3137 using FULL_CPU Mode with CPU Write to CRC, there is no pure 64-Bit write possible.

Right or wrong?

Thank you.

Regards

Pashan