• State TI Thinks Resolved
  • Locked Locked
  • Replies 4 replies
  • Answers 1 answer
  • Subscribers 32 subscribers
  • Views 481 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Bit setting time in TMS470PSF761A controller

Ranjitha Sreedharan
Prodigy 20 points

could you please let me know what will be the maximum taken by the controller to set a single bit for the controller mentioned in the subject?

  • 0
    TI__Intellectual 1480 points

    Ranjita,

    Can you clarify what you mean by  " maximum taken by the controller to set a single bit for the controller "

    -Hari

  • 0 in reply to Hari Pendurty
    Prodigy 20 points

    Hello Hari,

    It means that the time taken for a register bit to be set. For example if I set "INIT" bit of DCAN in TMS470 controller it will not be set immediately we would have to wait for a particular period of time so i would like to know what is the this wait time? This is dependent on the Clock frequency i guess so would like to know the correct value of that waiting time?

    Regards,

    Ranjitha

  • 0 in reply to Ranjitha Sreedharan
    TI__Guru 72500 points

    Ranjita,

    Sorry, it looks like your request was accidentally dropped. It is hard for me to be precise without running a design simulation. But a chalk board analysis of the bridge structure shows it would be 13 to 15 HCLK cycles assuming that VCLK=2*HCLK and that no other bus masters are accessing the peripherals. Often we recommend reading the peripheral after doing the write to insure that no additional CPU instruction are executed until after the write has completed.

  • 0 in reply to Bob Crosby
    TI__Guru 72500 points

    Ranjita,

    I got a more refined answer from one of the architects. With VCLK at half the frequency of HCLK and no bus confilicts that need to be arbitrated, it should be 9 or 10 HCLK cycles.