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Error using Self Test Controller

Cristiano Werner Araujo
Intellectual 280 points

Hello,

I'm trying to run the LBIST test using the Self Test Controller.

I enable it, set the clock and select a interval to run. I have putted the timout in the maximum available.

After it I enable it and enter the Core in Idle mode ( WFI instruction ).

The core reboots, but the reboot flag is not asserted and it runs as a simple reset.

I've tried to to debug the flag, but I'm always reading zero.

Thanks,

Cristiano

  • 0
    TI__Intellectual 1480 points

    Hi Cristiano,

    My suspicion self test mode configuration registers have not been programmed properly i the self test controller .  hence the self test is not enabled

    Could you check for the following

    - Are you entering into priviledged mode before configuring the STCGCR and STCTPR

    - What  values are you observing in the STCGSTAT register  for bit0 : Test_done and bit 1 Test_fail

    -Can you clarify what do you mean by the reboot  and reboot flag . are you referring to bit 5 of the SYSESR(CPU_RST status bit) as the reboot flag.

    - What values are you observing SYSESR register after the CPU reboots .

     

    -Hari

  • 0 in reply to Hari Pendurty
    Intellectual 280 points

    Hello Hari,

    thanks for the quick answer.

    I'm not entering in priviledged mode, I have searched for but I didn't finded how since I can write to the Mode field in the CPSR register.

    If you can show me how I would be thankful.

    I'm reading the Value 0x2008 in the SYSESR register, and yes, I mean it when I wroted "reboot flag".

    For what I can see in table 2-68 of the RM48 Reference Manual, the Bit 3 indicates SWRST and the Bit 13 indicates WDRST ( watchdog reset ).

    The values that I founded in the registers are bellow :

    STCGCR0 : 0xFFFF0000

    Self-test runned 0XFFF and will continue STC from previous interval

    STCGCR1 : 0x5

    Self-test Disabled.

    STCTPR : 0xFFFFFFFF

    Same as saved before calling.

  • 0 in reply to Cristiano Werner Araujo
    TI__Intellectual 1480 points

    Cristiano,

     Their could be 2 issues over based on what you have explained

    1) Either you entered in user mode by programming the mode bits in the CPSR before kicking off the self test.. As out of reset the CPU by default is in supervisor mode.

    If you are in user mode all writes to the configuration registers in the self test controller will be blocked

     OR

    2) While the Self test was running an system reset due to the watchdog or sourced from a software reset disabled the self test (as you observed in the SYSESR).

     As on a system reset  the self test will be disabled and all the self test controller registers will be set to their default state

     

    On how to enter supervisor mode i am providing you the same snippet i provided you for your question on CCMR4

    You can use the SuperVisor Call  (SVC) instruction (formerly SWI) to enter Supervisor mode,

    Please be aware that the use of SWI is deprecated on the v7R architecture (Cortex-R4(f)). It should be replaced by the SVC instruction in any code.

     To be able to cover both cases, following code snippet can be used:

    SUPERVISOR SERVICE ROUTINE
    svc:    STMFD       sp!, {r0-r12,lr}        ; Save registers on stack
             LDRB         r0, [lr,#-1]         ; Load the SVC-# into R0
    -----
    -----
    -----
             LDMFD   sp!, {r0-r12,pc}^   ; Restore registers and return
     
  • 0 in reply to Hari Pendurty
    TI__Intellectual 1480 points

    Cristiano,

    Can you verify the answer so that i can close the post.