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use uCOSII , modify Interrupt vector address occurred error

jianwei xie
Intellectual 305 points
Other Parts Discussed in Thread: HALCOGEN, RM48L950

Hi,

When use the micrum ucosII of RML48. at First ,the application run in flash is well.

But, I want  to run the OS in RAM , so I use the jlink to clear the flash and then modify the
default flash ICF file :

define symbol __ICFEDIT_intvec_start__ = 0x00000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x00000040;
define symbol __ICFEDIT_region_ROM_end__ = 0x002FFFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x08000000;
define symbol __ICFEDIT_region_RAM_end__ = 0x0803FFFF;

to RAM ICF:

define symbol __ICFEDIT_intvec_start__ = 0x08000000;
/*-Memory Regions-*/
define symbol __ICFEDIT_region_ROM_start__ = 0x08000040;
define symbol __ICFEDIT_region_ROM_end__ = 0x0801FFFF;
define symbol __ICFEDIT_region_RAM_start__ = 0x08020000;
define symbol __ICFEDIT_region_RAM_end__ = 0x0803FFFF;

but it will be occur exception,application can't running.

thanks a lot 

  • 0
    Intellectual 305 points

    I find some bug in my app.

    see the doc  , eg.

    The main flash instruction memory is addressed starting at 0x00000000 by default. This is also the reset
    vector location – the ARM Cortex-R4F processor core starts execution from the reset vector address of
    0x00000000 whenever the core gets reset.
    The CPU data RAM is addressed starting at 0x08000000 by default.
    The device also supports the swapping of the CPU instruction memory (flash) and data memory (RAM).
    This can be done by configuring the MEM SWAP field of the Bus Matrix Module Control Register 1
    (BMMCR1).

    i want use boot application to copy main application to RAM run , how can i swap memory to achieve this function?

  • 0 in reply to jianwei xie
    TI__Mastermind 22375 points

    jianwe,

    Thanks for using our forum.

    By default on the Hercules family, the Flash (program memory) is mapped to 0x0000_0000 and the internal RAM (Data RAM) is mapped to 0x0800_0000.

    As you mentioned, it is possible to swap the memory and mapped the RAM at 0x0000_0000 and Flash to 0x0800_0000.

    If I understand your question, you want to boot from Flash (at 0x0000_0000) and than copy your code in RAM (0x0800_0000) and execute from RAM.

    Also one important point is during the link time.
    It is necessary to inform the linker that the code will be loaded in flash, but executed from somewhere else.
    Here is an example of linker command doing this function:

    MEMORY
    {
        VECTORS (RX) : origin=0x00000000 length=0x00000100
        FLASH   (RX) : origin=0x00000100 length=0x00003f00
        FLASH1  (RX) : origin=0x00004000 length=0x00001000
        STACKS  (RW) : origin=0x08000000 length=0x00001000
        RAM     (RW) : origin=0x08001000 length=0x00004000
        RAM1    (RW) : origin=0x08005000 length=0x00004000


    /* USER CODE BEGIN (1) */
    /* USER CODE END */
    }

    SECTIONS
    {
        .text      : run  = FLASH,   load = FLASH
        .intvecs   : run  = FLASH,   load = FLASH
        .const     : run  = FLASH,   load = FLASH
        .cinit     : run  = FLASH,   load = FLASH
        .pinit     : run  = FLASH,   load = FLASH
        .bss       : {} > RAM
        UCOS      : { ucos.obj(.text),ucos.obj(.const)} run  = RAM1,    load = FLASH

    /* USER CODE BEGIN (2) */
        .sysmem : {} > RAM
    /* USER CODE END */
    }

    In this example, the section named UCOS (code and constant) will be loaded in flash, but executed from RAM1 (origin=0x08005000 length=0x00004000)

    At run time, you will have to execute a memcopy to "move" your the code and constant to be used from RAM.

    Please let me know if I've answered your question.

    Regards,

    Jean-Marc


  • 0 in reply to Jean-Marc Mifsud
    Intellectual 305 points

    Jean-Marc,

    we use IAR for development , and want use one Boot-loader  to load the app ;  we want use ISP to receive SCI  app.bin data and store it  in app  flash sector .

    the app will be copied to ram and  run .

  • 0 in reply to jianwei xie
    TI__Mastermind 22375 points

    jianwei,

    If I understand, the boot loader will receive your application via SCI and will program the code in internal flash.
    Than at run time, the boot loader will execute from flash and will copy the CPU Application to RAM and will execute it from RAM.

    I assume that IAR tool also provide a way to link your code with a load address and a run address.
    I will try to see if I can find anything in IAR documentation and I will be back to you.

    Thanks and Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 305 points

    Jean-Marc

    Yes . The boot loader run in flash ;  the application stored in internal flash will be copy to RAM to run.

    But I want to understand  two point question :

    1. application will be  stored  in flash , and  this application will be copy to RAM  to execute by boot loader in flash.  do this is feasible?

    2. the application can be debugged in RAM ?

    I have try to debug app in ram, but the app can't be executed .

       My configrtion of app in IAR is : invecter start at 0x0800-0000 ; code start at 0x0800-0040 , end at 0x0801-FFFF; RAM start at 0x0802-0000, end at 0x0803-FFFF.

      My application part of Map file is :

    "A1": place at   0x08000000     { ro section .intvec };
    "P1": place in   [from 0x08000040 to 0x0801ffff] { ro };
    "P2": place in   [from 0x08020000 to 0x0803ffff] {
    rw, block CSTACK, block SVC_STACK, block IRQ_STACK, block FIQ_STACK,
    block UND_STACK, block ABT_STACK, block HEAP };

    Section Kind     Address         Size           Object
    ------- ---- ------- ---- ------
    "A1": 0x40
    .intvec ro code   0x08000000 0x40          cstartup.o [1]
    - 0x08000040    0x40

    "P1": 0x9808
    .text ro code       0x08000040   0x1474    serial.o [1]
    .text ro code       0x080014b4   0x278      serial_os.o [1]
    .text ro code       0x0800172c   0x1140    lib_mem.o [1]
    CODE ro code  0x0800286c   0x260       cpu_a.o [1]
    .text ro code       0x08002acc   0x388       cpu_core.o [1]

    .........

     But i find the application run in error when the application have interrupt event . then i think there is something error with interrupt vector? )

    thanks a lot

    Jianwei


  • 0 in reply to jianwei xie
    TI__Mastermind 22375 points

    jianwei,

    I think I understand your problem and correct me if I'm wrong.

    Your are not using the swap mode, meaning that flash is still mapped to 0x000_0000 and RAM at 0x0800_0000 when you run your application.

    The exception table has to be loaded at 0x0000_0000. This is where the CPU will jump in case of Reset, IRQ, FIQ, Prefetch Abort, Data Abort, SWI and Undefined instruction. This is true whatever you run code from Flash or from RAM.

    I can see in your map file that the intvecs section is loaded at 0x0800_0000. This is not valid.

    How to you plan to use interrupts? The Hercules family supports 3 ways to handle interrupts.

    a) Legacy way, the CPU will jump at 0x18 for IRQ and 0x1C for FIQ. At these location, the CPU will find a branch to IRQ or FIQ handler.
         The IRQ and FIQ handler are a switch case, using the VIM_ Register to find out what was the cause of the interrupt.

    0x18   B IRQ_HANDLER
    0x1C  B FIQ_HANDLER

        In this mode, the VIM VECTOR RAM is not used.

    b) Vectored mode. In this mode the CPU will still jump to 0x18 or 0x1c, and will find an instruction like:

    0x18   LDR PC,[PC,#-0x1b0]
    0x1C   LDR PC,[PC,#-0x1b0]

        In this mode, the CPU will jump directly in your module_interrupt handler. All the base address of your interrupt handler have to be stored in the VIM RAM.

    c) VIC mode (Valid for IRQ only)
         This mode is not available after reset. The CPU has to enable this mode using CP15 (Halcogen can take care of this via the "R4-MPU-PMU" tab and selecting "Enable IRQ Handler via VIC Controller"). I can send you the asm code if you are interested.
         In this mode of operation, the CPU will not jump anymore to 0x18 in case of IRQ interrupt, but will jump directly in the ISR Handler. Here also the VIM RAM has to be loaded will all the base addresses for all your ISR Handler.

    I will suggest in your case to use the option 3.

    I have also a question for you. When you reset your device and start your application from the boot loader, do you have to support interrupt or not?

    Please let me know if you need more details.

    Regards,

    Jean-Marc

  • 0 in reply to Jean-Marc Mifsud
    Intellectual 305 points

    Jean-Marc

    Thank you for your useful reply. 

    The swap mode for ram and flash is my first choice  to achieve application run in ram  , but i don't find the swap step of RM48.

    If your can provide some suggest or example about  swap the ram and flash will be helpful for me,   Thanks again.

    Jianwei

  • 0 in reply to jianwei xie
    TI__Mastermind 22375 points

    jianwe,

    The swap mode cannot be used at run time. This more a debug mode where once your device is attached to a debugger you can swap Flash and RAM to load your code in RAM and not have to program the code in flash.

    On of the main draw back in this mode is, in case of reset, the device will switch back to "normal mode" meaning flash mapped to 0x0000_0000 and RAM to 0x0800_0000.

    So really for an application this has no real value.

    To clarify one point, moving code from Flash to RAM is definitively a valid option, and assuming you follow the load address/run address requirements, this is a fully supported method.
    Debugging code from RAM is even better. There is no limit on the number of break-point (software break-point) that can be used in RAM versus the 6 break-point available when debugging from Flash (hardware break-point).

    On RM48x devices, to swap the Flash and RAM please follow this sequence:

    1] Write 0x05 to BMMCR1 (0xFFFF_FFC4)    /* Swap Memory */
    2] Write 0x01 to MMUGCR (0xFFFF_FFCC)  /* Reset CPU only, the rest of the device is not affected */
    3] Write 0x00 to MMUGCR (0xFFFF_FFCC) 

    Again, this sequence cannot be executed at run time, this is only valid when the device is in debug mode.
    Note: In CCS, we provide a script to perform this swap. It is available at:

    Scripts->RM48L950 Memory Switch->Target_RAM_to_0x0

    Regards,

    Jean-Marc