Hi there,
Could you verify my understanding on the HET program execution of TMS570 below?
1) The HET program starts to be executed on the rising edge of loop resolution clock (LR clock), right?
2) Within each loop resolution period (LRP), each of the HET instructions are executed once by the HET state machine. The flow of execution is determined by the next address and conditional address. Am I right?
3) In Table 18-46 of TMS570 TRM (Page 1326), there is a column called Cycles during which an HET instruction is executed. Does this cycle mean VCLK2 clock or something else (e.g. HR clock or LR clock)? Is the HR clock mainly used to implement the hr_data field for the HR clock delay within one LRP?
4) Pin actions and events become effective on the next rising edge of the LR clock only (instead of VCLK2 or HR clock), right?
Thank you so much.
Brent Shen