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TMS470M SCICLEARINT register setting problem

Other Parts Discussed in Thread: TMS470MF06607

Hi Champs,

    I have a question regarding to the SCI module (or maybe the compiler?...)

    I found that when the CPU execute the following C statement, the SETINT register will be cleared by 2 bits but not 1 bit.

    I am very confused by this behavior.

         sciREG1->CLRINT |= 0x200;

    However, if I use the statement of "sciREG1->CLRINT = 0x200;" the SETINT  register will be cleared by only 1 bit.

    I am using TMS470 HDK board with TMS470MF06607 on it.

    CCS version V5.2.0.00069

    Compiler version: TI v4.9.5 (And I have also tried TI v5.0.0B1, but same result.)

    Debugger: Spectrum Digital XDS510USB Plus

    

    I have attached my code to this thread.

    

    

    1488.TMS470_sci.zip


    Could anybody help me with this problem?

  • Hello,

    First of all, thank you for a very thorough problem explanation.

    The registers labeled CLR and SET typically have a funny property -- a read of the register tells the status of that function while a write sets or clears the function. 

    In this case, the SETINT and CLEARINT registers both read the same value since they show the status of the SCI interrupt sources. (e.g. is SCICLRINT.0 reads as 1, it means that the break-detect interrupt is enabled.)  However, writing the value of this register back to itself has significantly different behavior for the SETINT and CLEARINT registers. A write-back of the SETINT register has no impact since it sets the interrupt sources that are already set; on the other hand, a writeback of the CLEARINT register clears all active interrupt sources since every enabled source (read as a 1) is cleared (because a write of 1 clears the source)!

    While this behavior may be a little confusing, it offers the advantage that you outlined in your post -- that you do not have to read-modify-write. Instead, a simple write of the desired bits sets/clears the appropriate interrupt sources.

    Regards,

    Forum Support

  • Hi Kevin,

        Thanks a lot for your reply.

        That is fully understood :).

    Best regards.

    Ma