~1 MHz input signal timing`

Charlie,

Can you check the loop resolution of the HET? ( HR Prescale Divide rate X Loop Resolution Prescale Divide rate X T(VCLK2))  The loop resolution period may be to large to sample the 1MHz clock.

Regards,

Forum Support

The HR Prescale Divide rate is 0.

The LRPD rate is 32.

Does this not grant maximum resolution?

Charlie,

You'll have something like 32 VCLK2 periods per loop. What is the VCLK2 frequency?

Regards,

Forum Support

80 MHz

Charlie,

Just to clarify:

GCLK and HCLK are running at 80MHz and the VCLK2 prescale is 0 (in CLKCNTRL register at 0xFFFF_FFD0). Can you confirm?

Regards,

Forum Support

VCLK2, which is inside the HET is divided down by the HR and LR prescalers.

These prescalers are controlled by the HETPFR which is set to 0x0000 0500

I don't know what the CLKCNTRL register is.

Charlie

Charlie,

Obviously the line of debug I am taking is that the input clock frequency might be grossly mis-sampled if the sampling frequency was not fast enough.  Given an 80MHz operation and a HET prescaler of 32, you have a loop resolution of 400ns (80MHz/32 = 2.5MHz) with finer resolution possible using the HR features. If, however, the VCLK2 frequency were prescaled from HCLK, you would be at 40MHz/32 (or slower).

The PLL synthesizes 80MHz from your oscillator. This frequency is supplied to GCLK (clocking CPU) and HCLK (clocking the System). The peripherals run off of VCLK which is a divided-down version of HCLK (could be /1). The only peripheral not clocked by VCLK is HET which is clocked by VCLK2 (again, a divided-down version of HCLK in which the prescale may be /1). This scheme is summarized in a graphical way on page 42 of the datasheet (SPNS157C  http://www.ti.com/lit/gpn/tms470mf06607).

From a high-level, VCLK2 is supplied to the HET, and you are completely correct to say that HETPFR controls the prescalers within the HET.

Assuming that the PLL really is synthesizing 80MHz and that the PLL is chosen as the clock source for the GCLK and HCLK domains, then all you need to do is check the VCLK2 prescaler in CLKCNTRL register. Can you interrogate the following registers:

GHVCLKSRC at 0xFFFF_FF48 -- you expect the lest significant byte to be 1 (indicating that the PLL is clocking GCLK and HCLK)  -- see Section 4.2.19 of spnu495a http://www.ti.com/litv/pdf/spnu495a

CLKCNTRL at 0xFFFF_FFD0 -- you expect the most significant byte to be 0 (indicating VCLK2 = HCLK/1) see Section 4.2.48 of spnu495a http://www.ti.com/litv/pdf/spnu495a

You might also want to check the PLL configuration register to make sure it is really configured to give you 80MHz... see Section 6.4.1.1 and 6.4.1.2 also in spnu495a.

Can you attach a project?

Regards,

Forum Support

First of all, it should be noted that the PCNT function is relatively accurate at a 500kHz or lower input frequency.

 I'm using HALCOGEN, so GHVCLKSRC and CLKCNTRL were set automatically..

Here is the stuff you asked for:

1. a view of the memory locations 0xFFFF_FF48  and  0xFFFF_FFD0 from Code Composer Studio (in hex):

2. My project:   

2438.CharlieTiming2.zip

NOTE: the first three sets of P,C,D words in het.c are the only relevant ones.  The instructions are CNT, ECNT, and BR respectively (BR branches to CNT). 

Charles,

On NHET, each instruction can generate an interrupt. There is a bit in the control field to do so.

The NHET can generate up to 32 interrupt based on instruction execution.
Interrupt 0 correspond to the first instruction in your NHET code.
Interrupt 1 correspond to the second instruction in your NHET code.
......
Interrupt 31 correspond to the 32nd instruction in your NHET code.

If you have more than 32 instructions in your NHET program, 2 instruction will be mapped to the same request.

Interrupt 0 correspond to the 33nd instruction in your NHET code.
Interrupt 1 correspond to the 34 instruction in your NHET code.
......

Interrupt 31 correspond to the 64 instruction in your NHET code.

Regards,

Jean-Marc

Charles,

Did my answer clarified your question concerning interrupts on NHET?

If yes, can you please mark this answer has "Verified Answer" so we can close this thread.

Thanks and Regards,

Jean-Marc