Hi there,
According to TMS570 TRM, bit 6 (FIQ) and bit 7 (IRQ) of the CPSR (Current Program Status Reg) should be set to 0 in order to enable interrupts. Since CPSR is in CPU, how can I have access to it by using C code instead of assembly code? The same question applies to R1 register of CP15 to enable hardware vectored interrupts (IRQ only).
Thanks a lot,
Brent Shen