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Where can I find the Cortex-R4 defined Configuration Details as implemented for TMS570?

Pashan None
Genius 5660 points
Other Parts Discussed in Thread: TMS570LS3137

Hello Support,

In the Cortex-R4 TRM, there is a section called :

A.3 Configuration signals

In the above mentioned section of Cortex-R4 TRM, there are many Build Time Signal Configuartions as defined to be set by TMS570 Device Integrator.

How can I get a list of Initialized Power On Reset Values of all those Signals as declared by TI for TMS570LS3137 device?

Some of the example signals are :  PARECCENRAM[2:0] , ERRENRAM[2:0],  CFGEE  and so on

Thank you.

Regards

Pashan

 

  • 0
    TI__Guru 59540 points

    Hello Pashan:

    Generally, we provide details in regard to default conditions in the device TRM although we may not relate them back to the specific Cortex-R4 TRM design signal names. As an example, the device TRM's discuss the default state of the R4 ECC logic for RAM and Flash ECC as disabled on power up and there would be no real need to know the low level signal configurations for this.

    In addition, I have fowarded your request to one of our system architecture experts in case there are further details they might be able to provide.

  • 0
    TI__Prodigy 255 points

    Hi Pashan,

    We are working on this document. Once it is finalized internally, we will publish it on TI Hercules forum.

    TMS570 devices are big endian - configured by CFGEE signal. TCM ports error correction is disabled at reset - configured by PARECCENRAM[2:0]. TCM ports error check is enabled - configured by ERRENRAM[2:0].

    Sincerely,

    B Chavali

  • 0 in reply to B Chavali
    Genius 5660 points

    Hello Chavali,

    Is this document available for me to use?

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Guru 68920 points

    Pashan,

    Bala left the team; so someone else needs to pick this up.

    Do you have a list of the tieoffs you are interested in?  I'm not sure what the document is that she was referring to...

    -Anthony

  • 0 in reply to Anthony F. Seely
    Genius 5660 points

    Hello Anthony,

    All the items as defined in ARM TRM related to Build Configuration.

    One example from ARM TRM is shown below for easier understanding.

    Thank you.
    Regards
    Pashan

  • 0 in reply to Pashan None
    TI__Guru 68920 points

    Pashan,

    Most are tied off.  A few go back to control bits in the system module.  For example, there is a bit in the system module that allows you to swap RAM and FLASH after the next warm reset.   In this case I listed the power on reset value.   Parity odd/even is also programmable but defaults to odd.    TEINIT is controlled by TI OTP but we program this for "ARM" mode on the TMS570LS3137.

    VINITHI    '0'  (Vectors at 0x00000000)
    CFGEE    '1'  Big Endian
    CFGIE    '1'  Big Endian
    INITRAMA   '1'  ATCM enabled at reset
    INITRAMB   '1'  BTCM enabled at reset
    LOCZRAMA   '1' after power on reset, REMAP bit in system
    TEINIT    '0' (OTP)
    CFGATCMSZ[3:0]  '1110'  8M (To cover ECC as well as Flash)
    CFGBTCMSZ[3:0]  '1110'  8M (To cover ECC area as well as RAM)
    CFGNMFI    '1'  FIQ is NMI
    ENTCM1IF   '1'  Enables B1TCM
    PARECCENRAM[2:0] '000' Parity/ECC defaults to disabled
    PARLVRAM   '1'  (Re-Programmable in System Module)
    ERRENRAM[2:0]  '111' External error enabled for ATCM, B0TCM, B1TCM
    RMWENRAM[1:0]  '10'  RMW on BTCM only
    SLBTCMSB   '0'   BTCM0,1 interleaved at bit [3]

    Best Regards,

    Anthony