• State Resolved
  • Locked Locked
  • Replies 3 replies
  • Subscribers 31 subscribers
  • Views 404 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Couldn't match spna160a.zip sys_esm.h ESM Register with TRM

Pashan None
Genius 5660 points

Hello Support,

In the spna106a.zip file containing sys_esm.h file shows the following REGISTER for ESM:

typedef volatile struct esmBase
{
    uint32_t EPENASET1;              /* 0x0000                 */
    uint32_t EPENACLR1;              /* 0x0004                 */
    uint32_t INTENASET1;             /* 0x0008                 */
    uint32_t INTENACLR1;             /* 0x000C                 */
    uint32_t INTLVLSET1;             /* 0x0010                 */
    uint32_t INTLVLCLR1;             /* 0x0014                 */
    uint32_t ESTATUS1[3U];           /* 0x0018, 0x001C, 0x0020 */
    uint32_t EPSTATUS;               /* 0x0024                 */
    uint32_t INTOFFH;                /* 0x0028                 */
    uint32_t INTOFFL;                /* 0x002C                 */
    uint32_t LTC;                    /* 0x0030                 */
    uint32_t LTCPRELOAD;             /* 0x0034                 */
    uint32_t KEY;                    /* 0x0038                 */
    uint32_t ESTATUS2EMU;            /* 0x003C                 */
    uint32_t EPENASET4;              /* 0x0040                 */
    uint32_t EPENACLR4;              /* 0x0044                 */
    uint32_t INTENASET4;             /* 0x0048                 */
    uint32_t INTENACLR4;             /* 0x004C                 */
    uint32_t INTLVLSET4;             /* 0x0050                 */
    uint32_t INTLVLCLR4;             /* 0x0054                 */
    uint32_t ESTATUS4[3U];           /* 0x0058, 0x005C, 0x0060 */
    uint32_t ESTATUS5EMU;            /* 0x0064                 */
} esmBASE_t;

I don't see the following Registers within spnu499.pdf TRM:

    uint32_t ESTATUS4[3U];           /* 0x0058, 0x005C, 0x0060 */
    uint32_t ESTATUS5EMU;            /* 0x0064                 */

Instead I see only one ESTATUS4 Register instead of 3 Registers.

Please help.

Thank you.

Regards

Pashan

 

  • 0
    TI__Mastermind 49120 points

    The ESM can support up to 64 channels for each of groups 1, 2, and 3. The LS31x only uses more than 32 channels for group1. Therefore, the group2 and group3 status egisters only show 32 channels.

  • 0 in reply to Sunil Oak
    Genius 5660 points

    Hello Sunil,

    Confused still.

    Is there any Register at address 0x64 offset for ESM?

    Is there any Register at address 0x5C and 0x60 offset for ESM?

    Please answer below every question for my easy understanding.

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Intellectual 2310 points

    Hi Pashan

    If the Group x(x=0, 1, 2) has lesser than or equal to 32 channels, then one register is sufficient and the other register does not get implemented.

    So to answer your question none of the registers at 0x64, 0x60 and 0x5c DO NOT exist in case the corresponding group has lesser than or equal to 32 channels which is true in your case. Now since Group 1 has more than 32 channels the register viz. ESMSR4 is applicable.

    Hope this answers your question.