Intermittent Data Abort Exception
Hi,
CCS 5.1.0.201201061800
CGT 4.7.1
TMS570LS31x Hercules Microcontroller Development Kit (HDK)
Spectrum Digital XDS510 USB Plus
I have an intermittent data abort exception occuring on the above platform, as follows:
1. Reliably after power on reset (S4 PORRST) no data abort exception (no JTAG connected).
2. Every say 1 in 20 warm reset (S3 RST) a data abort exception (no JTAG connected).
3. With JTAG connected, a data abort exception on every 'CPU Reset/Resume'.
My data abort exception handler simply calls standard startup code _c_int00(). Without JTAG connected, the application enters an infinite loop of data abort exception leading to startup through _c_int00() every say 1 in 20 warm reset (S3 RST). Subsequent warm reset (S3 RST) then ALWAYS fails with data abort. The system requires a power on reset (S4 PORRST) to get going again.
Using JTAG I have demonstrated that it is the data abort exception that is occuring (assuming of course that the fault is the same one with/without JTAG connected). The data abort exception occurs on innocuous peripheral register read/writes, always the same one within a particular application build (the causal register varying if I vary the application image by function delete etc). For example last instruction in the following code snippets:
2211 (regSciLin[SCI_LIN_MODULE_2_E]).SCIPIO0 = 0x00000000U;
0000c4e8: E58C413C STR R4, [R12, #316]
1889 if(0U == (regDmm.DMMGLBCTRL & 0x01000000U))
0000c470: E59FC1F4 LDR R12, $C$CON21
0000c474: E59C0000 LDR R0, [R12]
At breakpoint at the data abort exception vector (address 0x10), inspection of the ESM registers indicate that no error has been detected, and nERROR line is not asserted.
I have used HALCoGen as the basis for my startup code, particularly in PLL setup where we start at 5MHz before lock and then immediately switch to 160MHz.
I wonder if there is some borderline condition, maybe in parity or ECC setup that might be causing the problem, but I would expect ESM to pick this up. It is noteworthy that a PORRST does not cause a data abort exception but a RST does.
A final confusing point: I am sure that I have had the very same application running under JTAG control without data abort exception on every reset/resume. Could I have possibly damaged the hardware kit in some way that would lead to the symptoms I am seeing. I should note however that I have two HDK and witness the same behaviour on each, maybe I have damaged them both in the same way? Seems unlikely.
All suggestions are welcome, regards, Tony.
