Fast interrupt processing

Cor,

FIQ mode has R8 to R14_fiq registers (dedicated registers), that means, in your FIQ ISR, if you only use these registers there is no need to push them in the stack, and no need to pop them at the end of your ISR.

Note, on Hercules family, the FIQ is in fact NMI. Once the f bit in the CPSR is cleared to enable FIQ at CPU level, it can be set anymore.
So there is no way to mask FIQ once enable. Only a reset will re-set the f bit.

Cor,

This is part of CORTEX R4 programmers model.

Please have a look to ARM Technical Reference Manual (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0363e/index.html)
on  Figure 2.3. Register organization