New to NHET design, advice needed!

Alan,

Sorry for the late reply. We spent some time discussing your question because it is quite complicated.

First of all, there is no easy way to sample 4 NHET pins simultaneously and save the data to RAM. It is possible to do it using the DMM module in direct data mode with one sync signal. It is also possible using NHET to generate this sync signal from your TCLK. DMM module can automatically save data to RAM.

The period of of the clocks generated by NHET is determined by LRP (loop resolution period). The HR setting is only used for fine tuning the edge timing. LRP will become bigger if NHET performs more functions.

It seems that you want to interface TMS570 with a CCD camera. Do you expect the sync signals come from CCD or TMS570? We are willing to brainstorm some ideas if you can provide a detailed picture of this interface. Where do you plan to save the data, internal or external memory?

Thanks and regards,

Zhaohong

Zhaohong,

The ADC in question is the AD9978A, the data sync signals (grid signals VD and HD) will need to come from the TMS570.  After each HD signal the AD9978A will send a 14bit ADC value to the TMS570 via the LVDT388A.  The ADC data will initially be stored on the TMS570 and then transferred to an external system, it sounds like the DMM module is the best option where the NHET generates the transfer sync signal from the TCLK.  If it helps the data can be delayed in order for the TMS570 and TCLK signal to settle.

Regards,

Alan

Alan,

I did some calculation on what is achievable by NHET. Assume that HCLK (system clock) is 160 MHz,  VCLK = 80MHz. NHET instructions are run by VCLK.

To generate a continuous clock, 2 instructions (CNT and ECMP) are needed. To generate a pulse train based on this clock, 3 instructions (ECNT, ECMP, and move32) are needed. The LRP required for 5 instructions is 8 VCLK cycles. Therefore, the maximum achievable frequency is is 80/16 = 5 MHz.

If you also want to use the same NHET to generate the sync signal to read data, 3 more instruction is needed. a loop time of 16 VCLK may be needed. It will reduce the maximum frequency to 2.5 MHz. This also means that NHET can only capture an input clock up to 2.5 MHz.

You may consider use the second NHET to generate the sync. Since 3 instructions are needed, LRP will be 4 VCLK clocks. This will allow NHET to capture input upto 10 MHz. The two NHETs can be synchronized together. This is not fast enough to work with a 40 Mhz clock. You need to consider using a external counter to generate the sync to read the data at 40MHz.

Thanks and regards,

Zhaohong

Zhaohong,

That was a very helpful post, the generation of the HD and VD signal is not time critical and so could can be slowed down greatly, they could even be controlled by GIOs.  But from your post this still wont solve the problem of the data acquisition; could you expand on how I would go about using an external counter to generate the sync to read the data at 40MHz?  I'm not sure how this would be implemented.

Alan

Alan,

I have another idea. TMS570 can generate a continuous 40 MHz clock (ECLK) from the ECP module. From NHET, we can generate a 5 MHz clock with 12.5% duty using the HR structure. They will be synchronized because they are all driven by VCLK. Those two signals can be used at DMMCLK, and DMMSYNC. I think that it would work for you if your CCD sensor takes TCLK externally (use ECLK as TCLK).

Thanks and regards,

Zhaohong

Zhaohong,

Regarding the ADC/TMS570 the setup I have is best described by the image below which is taken from the AD9978 datasheet.

For the NHET to deal with the TCLK signal coming in it needs to generate a signal/loop internally which is equal to it? Within the loop 4 pins need to be checked twice and have their state stored on RAM or DMM.  This loop can not be done as there are too many instructions to carry out in the time given.  If it were possible how would the synchronicity be kept?

Are the above NHET considerations correct?

Alan

Alan,

As discussed earlier, there is no good way to use NHET to sample 4 pins and save their states to RAM. It is possible to use DMM module to sample the 4 pins and save the states to RAM. But DMM requires a sync signal. This sync signal needs to be synchronized with your TCLK (which is used as the data sample clock). I took a look at AD9978 data sheet. It is only one long without any details. I guess that CLI is the clock source for AD9978. What is the requirement? Can you send a link to a more detailed function spec?

Thanks and regards,

Zhaohong

Zhaohong, OK, I think I can get this to work, thankfully I can set up 16 control words before the data is sent, this should give me a way of making sure the clocks are in sync before the sampling of data, or alternatively de-scramble the data after it has been stored.  Unfortunately Analog Devices are very secretive over this device, they have watermarked my PDF so I would not like to leave it as a link in this forum. thanks, Alan.