STC - Configuration and Storage

Alex,

After LBIST completes, a CPU reset is triggered. None of the system/peripheral registers and RAM content is affected. From a user's perspective, only PC is changed to address 0x0. Nothing else is affected.

If you have not run LBIST before, I would recommend you first  try running the test from RAM. If you really want to run it from Flash, I would suggest using an I/O pin to control LBIST execution. If you allow LBIST to run automatically after CPU boots up, CPU will be locked in a reset->LBIST->reset-LBIST.. loop. You will not be able to connect CPU to CCS and reprogram the device.

Thanks and regards,

Zhaohong

Hi Zhaohong,

OK, I will give that a go, could you let me know where the golden MISR is created or how to find it?

Thanks in advance,

Alex

Alex,

The golden MISR is stored in STC ROM. It is not accessible from bench.

Thanks and regards,

Zhaohong

Hi Zhaohong,

I understand the MISR is based on a form of "Linear feedback shift register", how does it operator?

In the case where a single CPU fails does the opposite CPU not report the golden MISR in its CPU#_CURMISR registers?

If the next cycle takes the previous cycle as a starting point can the MISR not be worked out from the previous cycles data stored at the address in STC_CADDR or does each cycle calculate the MISR form a set of random data.

In figure 9.4 the flow chart alludes to some other module carrying out the same process to calculate the golden MISR before LBIST carries it out in order to define what the golden MISR is, how is this confirmed to be correct?

Cheers,

Alex

I'm also trying to get the code to program and run in RAM, I'm using the first method suggested by QJ Wang in this post http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/147475.aspx, I can also see no parts in my code which may cause the conflicts mentioned by Sunil Oak either.

However I'm having problems, the program seems to run straight away and there are breakpoint errors

CortexR4: Trouble Removing Breakpoint with the Action "Terminate Program Execution" at 0xf68: (Error -1066 @ 0xF68) Unable to set requested breakpoint in memory. Verify that the breakpoint address is in writable memory. (Release 5.0.429.0)
CortexR4: Trouble Removing Breakpoint with the Action "Finish Auto Run" at 0x368: (Error -1066 @ 0x368) Unable to set requested breakpoint in memory. Verify that the breakpoint address is in writable memory. (Release 5.0.429.0)

Any suggestion?

I wish to run both the LBIST an PBIST self tests at start up.  After the normal start up coded by Halcogen the TMS570 will initialise GPIO settin GPIOA6 low to inform the system that the TMS570 is undergoing its self test, this needs to stay low until the self tests, looking at the info in the TRM for both tests it looks like the pin should not be disturbed.

After the GPIO has been set the SYSESR register is serviced to see what had caused the restart (at the initial start up no bit should be set) this leads the TMS570 to start the PBIST test.

As the EMIF is not working on my device the PBIST will have to be separated, the first run will have the MBSPI test disabled so that the error data can be transferred when it occurs, the second run of the PBIST will be just for the MIBSPI with the data stored in RAM.

Once the PBIST is completed, how do i re-initialise te memory?

through placing "_memoryInit_();" in the code

Once PBISt is complete I will start LBIST, which once finished will restart the CPU, this means that the code will start at main() once more?

Assuming this is the case then I will need a flag so that PBIST will be skipped, would MSTDONE still be set to 1 after a LBIST reset?

Cheers,

Alex

Alex,

After running PBIST for ESRAM, all the RAM content is gone and you will not be any to continue the test. the approach we used in testing is to set up the DCAN RAM in test mode before starting PBIST. After PBIST is done, save the PBIST status to DCAN RAM and generate a S/W reset. If you use pointer in c-code to access PBIST registers, you will also need to set up the pointer as a "register". Please take a look at the example in the following thread.

http://e2e.ti.com/support/microcontrollers/hercules/f/312/t/210070.aspx

You need to reconfigure the PBIST RAM group ID and algorithm for your device. In this example, I also include test for enable MPU and reading the status back.

Please let me know if this example has all the information you need.

Thanks and regards,

Zhaohong

Alex,

What is the status on this thread?

Did we answered your question? If yes, can you mark it as "Verified Answer" so we can close this thread.