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How to determine eFuse Controller end of Initialization once PORRST^ is deasserted?

Pashan None
Genius 5660 points

Hello Support,

I am assuming that there is some CLOCK Cycles are required once PORRST^ Signal is DEASSERTED in order to eFuse Controoler allow its complete initialization?

Which Register Bit indicates that eFuse controller have initialized successfully or with ERROR after PORRST Signal is deasserted?

I am looking for some IN_PROGRESS eFuse Controller initialzation flag after Cold Reset.

Any information will be helpful.

Thank you.

Regards

Pashan

 

  • 0
    TI__Guru 59540 points

    Hello Pashan:

    eFuse autoload occurs at power up reset and is completed before the CPU is released from reset. If there are errors during eFuse initialization on power up, the system is notified within the ESM.

    The specific assignments to eFuse errors within the ESM are as follows:

    Group 1 channel 40: eFuse Controller Error– this error signal is generated when any bit in the eFuse controller error status register is set. The application can choose to generate an interrupt whenever this bit is set to service any eFuse controller error conditions.

    Group 1 channel 41: eFuse Controller - Self Test Error. This error signal is generated only when a self test on the eFuse controller generates an error condition. When this error signal is Group1 41 set, group 1 channel 40 error signal will also be set.

    Group 3 channel: eFuse Controller - autoload error

  • 0 in reply to Chuck Davenport
    Genius 5660 points

    Hello Chuck,

    So, after PORRST, when CPU reads EFCERRSTAT Register, Bit 5 will be always guranteed to be ONE.

    Is that correct?

    Or, I should see ZERO?

    Please help me understand Bit 5 functionality of EFCERRSTAT Register.

    Thank you.

    Regards

    Pashan

     

  • 0 in reply to Pashan None
    TI__Guru 59540 points

    Bit5 of the EFCERRSTAT register is used to indicate the status of a requested self test. On power up this bit is a default value of 0 but this does not necessarily indicate anything relavent since on power up there has not been any requested self test. I believe you are more interested in bits 4-0 of this register which will give the result of the autoload sequence. A value of 0 in the error  ode field on power up means that there were no errors encountered during autoload.

    Note that it is recommended that the application check the status of the eFuse controller after powerup. Details of this are provided in the TRM. Essentially this involves checking the status of the eFuse related channels in the ESM registers and  the efuse error status register to classify the type of failure that ocurred and which of the self-test algorithms to execute on the eFuse controller. A recommended flow is given in the TRM as well as instructions on how to run the self-tests.